计算机组成与设计:硬件/软件接口(英文版·第4版)(Patterson & Hennessy名著，MIPS版)[图书]

2.7 Instructions for Making Decisions 105
2.8 Supporting Procedures in Computer Hardware 112
2.9 Communicating with People 122
2.10 MIPS Addressing for 32-Bit Immediates and Addresses 128
2.11 Parallelism and Instructions: Synchronization 137
2.12 Translating and Starting a Program 139
2.13 A C Sort Example to Put It All Together 149
2.14 Arrays versus Pointers 157
2.15 Advanced Material: Compiling C and Interpreting Java
2.16 Real Stuff: ARM Instructions 161
2.17 Real Stuff: x86 Instructions 165
2.18 Fallacies and Pitfalls 174
2.19 Concluding Remarks 176
2.20 Historical Perspective and Further Reading 179
2.21 Exercises 179
3 Arithmetic for Computers 222
3.1 Introduction 224
3.2 Addition and Subtraction 224
3.3 Multiplication 230
3.4 Division 236
3.5 Floating Point 242
3.6 Parallelism and Computer Arithmetic: Associativity 270
3.7 Real Stuff: Floating Point in the x86 272
3.8 Fallacies and Pitfalls 275
3.9 Concluding Remarks 280
3.10 Historical Perspective and Further Reading 283
3.11 Exercises 283
4 The Processor 298
4.1 Introduction 300
4.2 Logic Design Conventions 303
4.3 Building a Datapath 307
4.4 A Simple Implementation Scheme 316
4.5 An Overview of Pipelining 330
4.6 Pipelined Datapath and Control 344
4.7 Data Hazards: Forwarding versus Stalling 363
4.8 Control Hazards 375
4.9 Exceptions 384
4.10 Parallelism and Advanced Instruction-Level Parallelism 391
4.11 Real Stuff: the AMD Opteron X4 (Barcelona) Pipeline 404
4.12 Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 406
4.13 Fallacies and Pitfalls 407
4.14 Concluding Remarks 408
4.15 Historical Perspective and Further Reading 409
4.16 Exercises 409
5 Large and Fast: Exploiting Memory Hierarchy 450
5.1 Introduction 452
5.2 The Basics of Caches 457
5.3 Measuring and Improving Cache Performance 475
5.4 Virtual Memory 492
5.5 A Common Framework for Memory Hierarchies 518
5.6 Virtual Machines 525
5.7 Using a Finite-State Machine to Control a Simple Cache 529
5.8 Parallelism and Memory Hierarchies: Cache Coherence 534
5.9 Advanced Material: Implementing Cache Controllers 538
5.10 Real Stuff: the AMD Opteron X4 (Barcelona) and Intel Nehalem Memory Hierarchies 539
5.11 Fallacies and Pitfalls 543
5.12 Concluding Remarks 547
5.13 Historical Perspective and Further Reading 548
5.14 Exercises 548
6 Storage and Other I/0 Topics 568
6.1 Introduction 570
6.2 Dependability, Reliability, and Availability 573
6.3 Disk Storage 575
6.4 Flash Storage 580
6.5 Connecting Processors, Memory, and I/O Devices 582
6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 586
6.7 I/O Performance Measures: Examples from Disk and File Systems 596
6.8 Designing an I/O System 598
6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 599
6.10 Real Stuff: Sun Fire x4150 Server 606
6.11 Advanced Topics: Networks 612
6.12 Fallacies and Pitfalls 613
6.13 Concluding Remarks 617
6.14 Historical Perspective and Further Reading 618
6.15 Exercises 619
7 Multicores, MulUprocessors, and Clusters 630
7.1 Introduction 632
7.2 The Difficulty of Creating Parallel Processing Programs 634
7.3 Shared Memory Multiprocessors 638
7.4 Clusters and Other Message-Passing Multiprocessors 641
7.5 Hardware Multithreading 645
7.6 SISD, MIMD, SIMD, SPMD, and Vector 648
7.7 Introduction to Graphics Processing Units 654
7.8 Introduction to Multiprocessor Network Topologies 660
7.9 Multiprocessor Benchmarks 664
7.10 Roofiine: A Simple Performance Model 667
7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 675
7.12 Fallacies and Pitfalls 684
7.13 Concluding Remarks 686
7.14 Historical Perspective and Further Reading 688
7.15 Exercises 688
APPENDICES
A Graphics and Computing GPUs A-2
A.1 Introduction A-3
A.2 GPU System Architectures A-7
A.3 Programming GPUs A-12
A.4 Multithreaded Multiprocessor Architecture A-25
A.5 Parallel Memory System A-36
A.6 Floating Point Arithmetic A-41
A.7 Real Stuff: The NVIDIA GeForce 8800 A-46
A.8 Real Stuff: Mapping Applications to GPUs A-55
A.9 Fallacies and Pitfalls A-72
A.10 Concluding Remarks A-76
A.11 Historical Perspective and Further Reading A-77
B Assemblers, Linkers, and the SPIM Simulator
B.1 Introduction B-3
B.2 Assemblers B-10
B.3 Linkers B-18
B.4 Loading B-19
B.5 Memory Usage B-20
B.6 Procedure Call Convention B-22
B.7 Exceptions and Interrupts B-33
B.8 Input and Output B-38
B.9 SPIM B-40
B.10 MIPS R2000 Assembly Language B-45
B.11 Concluding Remarks B-81
B.12 Exercises B-82
Index I-1
CD-ROM CONTENT
C The Basics of Logic Design C-2
C.1 Introduction C-3
C.2 Gates, Truth Tables, and Logic Equations C-4
C.3 Combinational Logic C-9
C.4 Using a Hardware Description Language C-20
C.5 Constructing a Basic Arithmetic Logic Unit C-26
C.6 Faster Addition: Carry Lookahead C-38
C.7 Clocks C-48
C.8 Memory Elements: Flip-Flops, Latches, and Registers C-50
C.9 Memory Elements: SRAMs and DRAMs C-58
C.10 Finite-State Machines C-67
C.11 Timing Methodologies C-72
C.12 Field Programmable Devices C-78
C.13 Concluding Remarks C-79
C.14 Exercises C-80
D Mapping Control to Hardware D-2
D.1 Introduction D-3
D.2 Implementing Combinational Control Units D-4
D.3 Implementing Finite-State Machine Control D-8
D.4 Implementing the Next-State Function with a Sequencer D-22
D.5 Translating a Microprogram to Hardware D-28
D.6 Concluding Remarks D-32
D.7 Exercises D-33
E A Survey of RISC Architectures for Desktop,Server, and Embedded Computers E-2
E.1 Introduction E-3
E.2 Addressing Modes and Instruction Formats E-5
E.3 Instructions: The MIPS Core Subset E-9
E.4 Instructions: Multimedia Extensions of the Desktop/Server RISCs E-16
E.5 Instructions: Digital Signal-Processing Extensions of the Embedded RISCs E-19
E.6 Instructions: Common Extensions to MIPS Core E-2(
E.7 Instructions Unique to MIPS-64 E-25
E.8 Instructions Unique to Alpha E-27
E.9 Instructions Unique to SPARC v.9 E-29
E.10 Instructions Unique to PowerPC E-32
E.11 Instructions Unique to PA-RISC 2.0 E-34
E.12 rnstructions Unique to ARM E-36
E.13 Instructions Unique to Thumb E-38
E.14 Instructions Unique to SuperH E-39
E.15 Instructions Unique to M32R E-40
E.16 Instructions Unique to MIPS-16 E-40
E.17 Concluding Remarks E-43
Glossary G-1
Further Reading FR-1

.　　Chapter 4: Parallelism and Advanced Instruction-Level Parallelism. It covers advanced ILP-superscalar, speculation, VLIW, loop-unrolling, and OOO-as well as the relationship between pipeline depth and power consumption.
　　Chapter5: Parallelism and Memory Hierarchies: Cache Coherence. It introduces coherency, consistency, and snooping cache protocols.
　　Chapter 6: Parallelism and I/O: Redundant Arrays of Inexpensive Disks. It describes RAID as a parallel I/O system as well as a highly available ICO system.
　　Chapter 7 concludes with reasons for optimism why this foray into parallelism should be more successful than those of the past.
　　I am particularly excited about the addition of an appendix on Graphical Processing Units written by NVIDIA's chief scientist, David Kirk, and chief archi-tect, John Nickolls. Appendix A is the first in-depth description of GPUs, which is a new and interesting thrust in computer architecture. The appendix builds upon the parallel themes of this edition to present a style of computing that allows the programmer to think MIMD yet the hardware tries to execute in SIMD-style whenever possible. As GPUs are both inexpensive and widely available--they are even found in many laptops--and their programming environments are freely available, they provide a parallel hardware platform that many could experiment with.
　　The second goal was to streamline the book to make room for new material in parallelism. The first step was simply going through all the paragraphs accumulated over three editions with a fine-toothed comb to see if they were still necessary. The coarse-grained changes were the merging of chapters and dropping of topics. Mark Hill suggested dropping the multicycle processor implementation and instead adding a multicycle cache controller to the memory hierarchy chapter. This allowed the processor to be presented in a single chapter instead of two, enhancing the processor material by omission. The performance material from a separate chapter in the third edition is now blended into the first chapter.
　　The third goal was to improve the pedagogy of the book. Chapter 1 is now meatier, including performance, integrated circuits, and power, and it sets the stage for the rest of the book. Chapters 2 and 3 were originally written in an evolutionary style, starting with a "single celled" architecture and ending up with the full MIPS architecture by the end of Chapter 3. This leisurely style is not a good match to the modern reader. This edition merges all of the instruction set material for the integer instructions into Chapter 2-making Chapter 3 optional for many readers--and each section now stands on its own. The reader no longer needs to read all of the preceding sections. Hence, Chapter 2 is now even better as a reference than it was in prior editions. Chapter 4 works better since the processor is now a single chapter, as the multicycle implementation is a distraction today. Chapter 5 has a new section on building cache controllers, along with a new CD section containing the Verilog code for that cache.
　　The accompanying CD-ROM introduced in the third edition allowed us to reduce the cost of the book by saving pages as well as to go into greater depth ontopics that were of interest to some but not all readers. Alas, in our enthusiasm to save pages, readers sometimes found themselves going back and forth between the CD and book more often than they liked. This should not be the case in this edition. Each chapter now has the Historical Perspectives section on the CD and four chapters also have one advanced material section on the CD. Additionally, all exercises are in the printed book, so flipping between book and CD should be rare in this edition.
　　For those of you who wonder why we include a CD-ROM with the book, the answer is simple: the CD contains content that we feel should be easily and immediately accessible to the reader no matter where they are. If you are interested in the advanced content, or would like to review a VHDL tutorial (for example), it is on the CD, ready for you to use. The CD-ROM also includes a feature that should greatly enhance your study of the material: a search engine is included that allows you to search for any string of text, in the printed book or on the CD itself. If you are hunting for content that may not be included in the book's printed index, you can simply enter the text you're searching for and the page number it appears on will be displayed in the search results. This is a very useful feature that we hope you make frequent use of as you read and review the book.
　　This is a fast-moving field, and as is always the case for our new editions, an important goal is to update the technical content. The AMD Opteron X4 model 2356 (code named "Barcelona") serves as a running example throughout the book,and is found in Chapters 1, 4, 5, and 7. Chapters 1 and 6 add results from the new power benchmark from SPEC. Chapter 2 adds a section on the ARM architec-ture, which is currently the world's most popular 32-bit ISA. Chapter 5 adds a new section on Virtual Machines, which are resurging in importance. Chapter 5 has detailed cache performance measurements on the Opteron X4 multicore and a few details on its rival, the Intel Nehalem, which will not be announced until after this edition is published. Chapter 6 describes Flash Memory for the first time as well as a remarkably compact server from Sun, which crams 8 cores, 16 DIMMs,and 8 disks into a single 1U bit. It also includes the recent results on long-term disk failures. Chapter 7 covers a wealth of topics regarding parallelism--including multithreading, SIMD, vector, GPUs, performance models, benchmarks, multipro-cessor networks--and describes three multicores plus the Opteron X4: Intel Xeon model e5345 (Clovertown), IBM Cell model QS20, and the Sun Microsystems T2 model 5120 (Niagara 2).
　　The final goal was to try to make the exercises useful to instructors in this Internet age, for homework assignments have long been an important way to learn material. Alas, answers are posted today almost as soon as the book appears. We have a two-part approach. First, expert contributors have worked to develop entirely new exercises for each chapter in the book. Second, most exercises have a qualitative description supported by a table that provides several alternative quantitative parameters needed to answer this question. The sheer number plus flexibility in terms of how the instructor can choose to assign variations of exercises will make it hard for students to find the matching solutions online. Instructors will also be able to change these quantitative parameters as they wish, again frustrating those students who have come to rely on the Internet to provide solutions for a static and unchanging set of exercises. We feel this new approach is a valuable new addition to the book--please let us know how well it works for you, either as a student or instructor!
　　We have preserved useful book elements from prior editions. To make the book work better as a reference, we still place definitions of new terms in the margins at their first occurrence. The book element called "Understanding Program Per-formance" sections helps readers understand the performance of their programs and how to improve it, just as the "Hardware/Software Interface" book element helped readers understand the tradeoffs at this interface. "The Big Picture" section remains so that the reader sees the forest even despite all the trees. "Check Yourself" sections help readers to confirm their comprehension of the material on the first time through with answers provided at the end of each chapter. This edition also includes the green MIPS reference card, which was inspired by the "Green Card" ofthe IBM System/360. The removable card has been updated and should be a handyreference when writing MIPS assembly language programs.
　　Instructor Support
　　We have collected a great deal of material to help instructors teach courses using this book. Solutions to exercises, chapter quizzes, figures from the book, lecture notes,lecture slides, and other materials are available to adopters from the publisher.Check the publisher's Web site for more information:
　　textbooks, elsevier, com/9780123744937
　　Concluding Remarks
　　If you read the following acknowledgments section, you will see that we went to great lengths to correct mistakes. Since a book goes through many printings, we have the opportunity to make even more corrections. Ifyou uncover any remaining,resilient bugs, please contact the publisher by electronic mail at cod4bugs@rnkp.corn or by low-tech mail using the address found on the copyright page.
　　This edition marks a break in the long-standing collaboration between Hennessy and Patterson, which started in 1989. The demands of running one of the world's great universities meant that President Hennessy could no longer make the sub-stantial commitment to create a new edition. The remaining author felt like a jug-gler who had always performed with a partner who suddenly is thrust on the stage as a solo act. Hence, the people in the acknowledgments and Berkeley colleagues played an even larger role in shaping the contents of this book. Nevertheless, this time around there is only one author to blame for the new material in what you are about to read.
　　Acknowledgments for the Fourth Edition
　　I'd like to thank David Kirk, John Nickolls, and their colleagues at NVIDIA (Michael Garland, John Montrym, Doug Voorhies, Lars Nyland, Erik Lindholm, Paulius Micikevicius, Massimiliano Fatica, Stuart Oberman, and Vasily Volkov) for writing the first in-depth appendix on GPUs. I'd like to express again my appreciation to Jim Larus of Microsoft Research for his willingness in contributing his expertise on assembly language programming, as well as for welcoming readers of this book to use the simulator he developed and maintains.
　　I am also very grateful for the contributions of the many experts who developed the new exercises for this new edition. Writing good exercises is not an easy task,and each contributor worked long and hard to develop problems that are both challenging and engaging:
　　Chapter 1: Javier Bruguera (Universidade de Santiago de Compostela)
　　Chapter 2: John Oliver (Cai Poly, San Luis Obispo), with contributions from Nicole Kaiyan (University of Adelaide) and Milos Prvulovic (Georgia Tech)
　　Chapter 3: Matthew Farrens (University of California, Davis)
　　Chapter 4: Milos Prvulovic (Georgia Tech)
　　Chapter 5: Jichuan Chang, Jacob Leverich, Kevin Lim, and Partha Ranganathan (all from Hewlett-Packard), with contributions from Nicole Kaiyan (University of Adelaide)
　　Chapter 6: Perry Alexander (The University of Kansas)
　　Chapter 7: David Kaeli (Northeastern University)
　　Peter Ashenden took on the Herculean task of editing and evaluating all of the new exercises. Moreover, he even added the substantial burden of developing the companion CD and new lecture slides.
　　Thanks to David August and Prakash Prabhu of Princeton University for their work on the chapter quizzes that are available for instructors on the publisher's Web site.
　　I relied on my Silicon Valley colleagues for much of the technical material that this book relies upon:
　　AMD--for the details and measurements of the Opteron X4 (Barcelona):William Brantley, Vasileios Liaskovitis, Chuck Moore, and Brian Waldecker.
　　Intel--for the prereleased information on the Intel Nehalem: Faye Briggs.
　　Micron--for background on Flash Memory in Chapter 6: Dean Klein.
　　Sun Microsystems--for the measurements of the instruction mixes for the SPEC2006 benchmarks in Chapter 2 and details and measurements of the Sun Server x4150 in Chapter 6: Yan Fisher, John Fowler, Darryl Gove, Paul Joyce, Shenik Mehta, Pierre Reynes, Dimitry Stuve, Durgam Vahia, and David Weaver.
　　U.C. Berkeley--Krste Asanovic (who supplied the idea for software concurrency versus hardware parallelism in Chapter 7), James Demmel and Velvel Kahan (who commented on parallelism and floating-point calculations), Zhangxi Tan (who designed the cache controller and wrote the Verilog for it in Chapter 5), Sam Williams (who supplied the roofline model and the multicore measurements in Chapter 7), and the rest of my colleagues in the Par Lab who gave extensive suggestions and feedback on parallelism topics found throughout the book.
　　I arb grateful to the many instructors who answered the publisher's surveys, reviewed our proposals, and attended focus groups to analyze and respond to our plans for this edition. They include the following individuals: Focus Group: Mark Hill (University of Wisconsin, Madison), E.J. Kim (Texas A&M University), Jihong Kim (Seoul National University), Lu Peng (Louisiana State University), Dean Tullsen (UC San Diego), Ken Vollmar (Missouri State University), David Wood (University of Wisconsin, Madison), Ki Hwan Yum (University of Texas, San Antonio); Surveys and Reviews: Mahmoud Abou-Nasr (Wayne State University), PerryAlexander (The University of Kansas), Hakan Aydin (George Mason University), Hussein Badr (State University of New York at Stony Brook), Mac Baker (Virginia Military Institute),Ron Barnes (George Mason University), Douglas Blough (Georgia Institute of Technology), Kevin Bolding (Seattle Pacific University), Miodrag Bolic (University of Ottawa), John Bonomo (Westminster College), Jeff Braun (Montana Tech), Tom Briggs (Shippensburg University), Scott Burgess (Humboldt State University), Fazli Can (Bilkent University), Warren R. Carithers (Rochester Institute of Technology),Bruce Carlton (Mesa Community College), Nicholas Carter (University of Illinois at Urbana-Champaign), Anthony Cocchi (The City University of New York), Don Cooley (Utah State University), Robert D. Cupper (Allegheny College), Edward W.Davis (North Carolina State University), Nathaniel J. Davis (Air Force Institute of Technology), Molisa Derk (Oklahoma City University), Derek Eager (University of Saskatchewan), Ernest Ferguson (Northwest Missouri State University), Rhonda Kay Gaede (The University of Alabama), Etienne M. Gagnon (UQAM), Costa Gerousis (Christopher Newport University), Paul Gillard (Memorial University of Newfoundland), Michael Goldweber (Xavier University), Georgia Grant (College of San Mateo), Merrill Hall (The Master's College), Tyson Hall (Southern Adventist University), Ed Harcourt (Lawrence University), Justin E. Harlow (University of South Florida), Paul F. Hemler (Hampden-Sydney College), Martin Herbordt (Boston University), Steve J. Hodges (Cabrillo College), Kenneth Hopkinson (Cornell University), Dalton Hunkins (St. Bonaventure University), Baback Izadi (State University of New York--New Paltz), Reza Jafari, Robert W. Johnson (Colorado Technical University), Bharat Joshi (University of North Carolina,Charlotte), Nagarajan Kandasamy (Drexel University), Rajiv Kapadia, Ryan Kastner (University of California, Santa Barbara), Jim Kirk (Union University),Geoffrey S. Knauth (Lycoming College), Manish M. Kochhal (Wayne State), Suzan Koknar-Tezel (Saint Joseph's University), Angkul Kongmunvattana (Columbus State University), April Kontostathis (Ursinus College), Christos Kozyrakis (Stanford University), Danny Krizanc (Wesleyan University), Ashok Kumar,S. Kumar (The University of Texas), Robert N. Lea (University of Houston),Baoxin Li (Arizona State University), Li Liao (University of Delaware), Gary Livingston (University of Massachusetts), Michael Lyle, Douglas W. Lynn (Oregon Institute of Technology), Yashwant K Malaiya (Colorado State University), Bill Mark (University of Texas at Austin), Ananda Mondal (Claflin University), Alvin Moser (Seattle University), Walid Najjar (University of California, Riverside),Danial J. Neebel (Loras College), John Nestor (Lafayette College), Joe Oldham (Centre College), Timour Paltashev, James Parkerson (University of Arkansas), Shaunak Pawagi (SUNY at Stony Brook), Steve Pearce, Ted Pedersen (University of Minnesota), Gregory D Peterson (The University of Tennessee), Dejan Raskovic (University of Alaska, Fairbanks) Brad Richards (University of Puget Sound),Roman Rozanov, Louis Rubin field (Villanova University), Md Abdus Salam (Southern University), Augustine Samba (Kent State University), Robert Schaefer (Daniel Webster College), Carolyn J. C. Schauble (Colorado State University), Keith Schubert (CSU San Bernardino), William L. Schultz, Kelly Shaw (University of Richmond), Shahram Shirani (McMaster University), Scott Sigman (Drury University), Bruce Smith, David Smith, Jeff W. Smith (University of Georgia, Athens), Philip Snyder (Johns Hopkins University), Alex Sprintson (Texas A&M), Timothy D. Stanley (Brigham Young University), Dean Stevens (Morningside College), Nozar Tabrizi (Kettering University), Yuval Tamir (UCLA), Alexander Taubin (Boston University), Will Thacker (Winthrop University), Mithuna Thottethodi (Purdue University), Manghui Tu (Southern Utah University), Rama Viswanathan (Beloit College), Guoping Wang (Indiana-Purdue University),Patricia Wenner (Bucknell University), Kent Wilken (University of California, Davis), David Wolfe (Gustavus Adolphus College), David Wood (University of Wisconsin, Madison), Mohamed Zahran (City College of New York), Gerald D. Zarnett (Ryerson University), Nian Zhang (South Dakota School of Mines & Technology), Jiling Zhong (Troy University), Huiyang Zhou (The University of Central Florida), Weiyu Zhu (Illinois Wesleyan University).
　　I would especially like to thank the Berkeley people who gave key feedback for Chapter 7 and Appendix A, which were the most challenging pieces to write for this edition: Krste Asanovic, Christopher Batten, Rastilav Bodik, Bryan Catanzaro, Jike Chong, Kaushik Data, Greg Giebling, Anik Jain, Jae Lee, Vasily Volkov, and Samuel Williams.
　　A special thanks also goes to Mark Smotherman for making multiple passes to find technical and writing glitches that significantly improved the quality of this edition. He played an even more important role this time given that this edition was done as a solo act.
　　We wish to thank the extended Morgan Kaufmann family for agreeing to publish this book again under the able leadership of Denise Penrose. Nathaniel McFadden was the developmental editor for this edition and worked with me weekly on the contents of the book. Kimberlee Honjo coordinated the surveying of users and their responses.
　　Dawnmarie Simpson managed the book production process. We thank also the many freelance vendors who contributed to this volume, especially Alan Rose of Multiscience Press and diacriTech, our compositor.
　　The contributions of the nearly 200 people we mentioned here have helped make this fourth edition what I hope will be our best book yet. Enjoy!
　　David A. Patterson