现代处理器设计(英文影印版)
基本信息
- 原书名: Modern Processor Design: Fundamentals of Superscalar Processors
- 原出版社: McGraw-Hill Science/Engineering/Math
- 作者: (美)John.P.Shen Mikko Lipasti [作译者介绍]
- 丛书名: 大学计算机教育国外著名教材系列(影印版)
- 出版社:清华大学出版社
- ISBN:9787302153573
- 上架时间:2007-7-30
- 出版日期:2007 年8月
- 开本:16开
- 页码:642
- 版次:1-1
- 所属分类:
计算机 > 计算机组织与体系结构 > 微处理器/CPU
教材 > 研究生/本科/专科教材 > 工学 > 计算机
教材 > 计算机教材 > 本科/研究生 > 计算机专业教材 > 计算机专业课程 > 计算机组成原理
教材 > 教材汇编分册 > 高等理工
本版教材征订号:0044092714-3
内容简介回到顶部↑
本书是关于处理器设计的最新、最权威教材,主要论述了:(1)处理器的设计方法和原理;(2)流水线技术;(3)主存与i/o系统;(4)超标量组织与技术;(5)powerpc 620和intcl p6等示例;(6)超标量处理器设计;(7)先进的指令流技术、存储器数据流技术;(8)多线程技术等。
本书适合作为计算机及相关专业的“处理器设计”课程的教材,也是有关专业人员很有价值的参考用书。
作者简介:
john paul shen is the director of intel's microarchitecture research lab (mrl), providing leadership to about two-dozen highly skilled researchers located in santa clara, ca; hillsboro, or; and austin, tx. mrl is responsible for de- veloping innovative microarchitecture techniques that can potentially be used in future microprocessor products from intel. mrl researchers collaborate closely with microarchi-tects from product teams in joint advanced-development efforts. mrl frequently hosts visiting faculty and ph.d.interns and conducts joint research projects with academic research groups.
prior to joining intel in 2000, john was a professor in the electrical and computer engineering department of carnegie mellon university, where he headed up the cmu microarchitecture research team (cmuart). he has supervised a total of 16 ph.d. students during his years at cmu.seven are currently with intel, and five have faculty positions in academia. he won multiple teaching awards at cmu. he was an nsf presidential young investigator.he is an ieee fellow and has served on the program committees of isca, micro,hpca, asplos, pact, iccd, itc, and ffcs.
he has published over 100 research papers in diverse areas, including fault-tolerant computing, built-in self-test, process defect and fault analysis, concurrenterror detection, application-specific processors, performance evaluation, compila-tion for instruction-level parallelism, value locality and prediction, analytical mod-eling of superscalar processors, systematic microarchitecture test generation, per-formance simulator validation, precomputation-based prefetching, database workload analysis, and user-level helper threads.
john received his m.s. and ph.d. degrees from the university of southern california, and his b.s. degree from the university of michigan, all in electrical engineering. he attended kimball high school in royal oak, michigan. he is happily married and has three daughters. his family enjoys camping, road trips, and reading the lord of the rings.
本书适合作为计算机及相关专业的“处理器设计”课程的教材,也是有关专业人员很有价值的参考用书。
作者简介:
john paul shen is the director of intel's microarchitecture research lab (mrl), providing leadership to about two-dozen highly skilled researchers located in santa clara, ca; hillsboro, or; and austin, tx. mrl is responsible for de- veloping innovative microarchitecture techniques that can potentially be used in future microprocessor products from intel. mrl researchers collaborate closely with microarchi-tects from product teams in joint advanced-development efforts. mrl frequently hosts visiting faculty and ph.d.interns and conducts joint research projects with academic research groups.
prior to joining intel in 2000, john was a professor in the electrical and computer engineering department of carnegie mellon university, where he headed up the cmu microarchitecture research team (cmuart). he has supervised a total of 16 ph.d. students during his years at cmu.seven are currently with intel, and five have faculty positions in academia. he won multiple teaching awards at cmu. he was an nsf presidential young investigator.he is an ieee fellow and has served on the program committees of isca, micro,hpca, asplos, pact, iccd, itc, and ffcs.
he has published over 100 research papers in diverse areas, including fault-tolerant computing, built-in self-test, process defect and fault analysis, concurrenterror detection, application-specific processors, performance evaluation, compila-tion for instruction-level parallelism, value locality and prediction, analytical mod-eling of superscalar processors, systematic microarchitecture test generation, per-formance simulator validation, precomputation-based prefetching, database workload analysis, and user-level helper threads.
john received his m.s. and ph.d. degrees from the university of southern california, and his b.s. degree from the university of michigan, all in electrical engineering. he attended kimball high school in royal oak, michigan. he is happily married and has three daughters. his family enjoys camping, road trips, and reading the lord of the rings.
作译者回到顶部↑
本书提供作译者介绍
John Paul Shen is the Director of Intel's MicroarchitectureResearch Lab (MRL), providing leadership to about two-dozen highly skilled researchers located in Santa Clara, CA;Hillsboro, OR; and Austin, TX. MRL is responsible for de-veloping innovative microarchitecture techniques that canpotentially be used in future microprocessor products fromIntel. MRL researchers collaborate closely with microarchi-tects from product teams in joint advanced-dev.. << 查看详细
目录回到顶部↑
table of contents
additional resources
preface
1 processor design
1.1 the evolution of microprocessors
1.2 instruction set processor design
1.2.1 digital systems design
1.2.2 architecture, implementation, and realization
1.2.3 instruction set architecture
1.2.4 dynamic-static interface
1.3 principles of processor performance
1.3.1 processor performance equation
1.3.2 processor performance optimizations
1.3.3 performance evaluation method
1.4 instruction-levelparallel processing
1.4.1 from scalar to superscalar
1.4.2 limits of instruction-level parallelism
1.4.3 machines for instruction-level parallelism
1.5 summary
2 pipelined processors
additional resources
preface
1 processor design
1.1 the evolution of microprocessors
1.2 instruction set processor design
1.2.1 digital systems design
1.2.2 architecture, implementation, and realization
1.2.3 instruction set architecture
1.2.4 dynamic-static interface
1.3 principles of processor performance
1.3.1 processor performance equation
1.3.2 processor performance optimizations
1.3.3 performance evaluation method
1.4 instruction-levelparallel processing
1.4.1 from scalar to superscalar
1.4.2 limits of instruction-level parallelism
1.4.3 machines for instruction-level parallelism
1.5 summary
2 pipelined processors








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