数字逻辑基础与Verilog设计（英文影印版）

.chapter 3
implementation technology
3.1 transistor switches
3.2 nmos logic gates
3.3 cmos logic gates
3.4 negative logic system
3.5 standard chips
3.6 programmable logic devices
3.7 custom chips, standard cells, and gate arrays
3.8 practical aspects
3.9 transmission gates
3.10 implementation details for splds, cplds,and fpgas
3.11 concluding remarks
chapter 4
optimized implementation of logic functions
4.1 karnaugh map
4.2 strategy for minimization
4.3 minimization of product-of-sums forms
4.4 incompletely specified functions
4.5 multiple-output circuits
4.6 multilevel synthesis
4.7 analysis of multilevel circuits
4.8 cubical representation
4.9 a tabular method for minimization
4.10 a cubical technique for minimization
4.11 practical considerations
4.12 cad tools
4.13 concluding remarks
chapter 5
number representation and arithmetic circuits
5.1 positional number representation
5.2 addition of unsigned numbers
5.3 signed numbers
5.4 fast adders
5.5 design of arithmetic circuits using cad tools
5.6 multiplication
5.7 other number representations
5.8 ascii character code
chapter 6
combinational-circuit building blocks
6.1 multiplexers
6.2 decoders
6.3 encoders
6.4 code converters
6.5 arithmetic comparison circuits
6.6 verilog for combinational circuits
6.7 concluding remarks
chapter 7
flip-flops, registers,counters, ano a simple processor
7.1 basic latch
7.2 gated sr latch
7.3 gated d latch
7.4 master-slave and edge-triggered d hip-flops
7.5 t hip-flop
7.6 jk flip-hop
7.7 summary of terminology
7.8 registers
7.9 counters
7.10 reset synchronization
7.11 other types of counters
7.12 using storage elements with cad tools
7.13 using registers and counters with cad tools
7.14 design examples
7.15 concluding remarks
chapter 8
synchronous sequential circuits
8.1 basic design steps
8.2 state-assignment problem
8.3 mealy state model
8.4 design of finite state machines using cad
tools
8.5 serialadder example
8.6 state minimization
8.7 design of a counter using the sequential circuit approach..
8.8 fsm as an arbiter circuit
8.9 analysis of synchronous sequential circuits
8.10 algorithmic state machine (asm) charts
8.11 formal model for sequential cimuits
8.12 concluding remarks chapter 9
asynchronous sequential circuits
9.1 asynchronous behavior
9.2 analysis of asynchronous circuits
9.3 synthesis of asynchronous circuits
9.4 state reduction
9.5 state assignment
9.6 hazards
9.7 a complete design example
9.8 concluding remarks
chapter 10
digital system design
10.1 building block circuits
10.2 design examples
10.3 clock synchronization
10.4 concluding remarks
chapter 11
testing of logic circuits
11.1 fault model
11.2 complexity of a test set
11.3 path sensitizing
11.4 circuits with tree structure
11.5 random tests
11.6 testing of sequential circuits
11.7 built-in self-test
11.8 printed circuit boards
11.9 concluding remarks
appendix a
verilog reference
a.i documentation in vefilog code
a.2 white space
a.3 signals in vefilog code
a.4 identifier names
a.5 signal values, numbers, and parameters
a.6 net and variable types
a.7 operators
a.8 verilog module
a.9 gate lnstantiations
a.10 concurrent statements
a.11 procedural statements
a.12 using subcircuits
a.13 functions and tasks
a.14 sequential circuits
a.15 guidelines,for writing verilog code
a.16 max+plusli verilog support
a.17 concluding remarks
appendix b
tutorial 1
b.1 introduction
b.2 design entry using schematic capture
b.3 design entry using verilog
b.4 design entry using truth tables
b.5 mixing design-entry methods
appendix c
tutorial 2
c.1 implementing a circuit
c.2 implementing a circuit in a flex 10k fpga
c.3 downloading a circuit into a device
c.4 making pin assignments
c.5 concluding remarks
appendix d
tutorial 3
d.i design using verilog code
d.2 using an lpm module
d.3 design of a sequential circuit
d.4 design of a finite state machine
d.5 concluding remarks
appendix e
commercial devices
e.1 simple plds
e.2 complex plds
e.3 field-programmable gate arrays
e.4 transistor-transistor logic
index...

.　　Asynchronous sequential circuits are discussed in Chapter 9. While this treatment is not exhaustive, it provides a good indication of the main characteristics of such circuits.Even though the asynchronous circuits are not used extensively in practice, they should be studied because they provide an excellent vehicle for gaining a deeper understanding of the operation of digital circuits in general. They illustrate the consequences of propagation delays and race conditions that may be inherent in the structure of a circuit.
　　Chapter 10 is a discussion of a number of practical issues that arise in the design of real systems. It highlights problems often encountered in practice and indicates how they can be overcome. Examples of larger circuits illustrate a hierarchical approach ha designing digital systems. Complete Verilog code for these circuits is presented.
　　Chapter ! 1 introduces the topic of testing. A designer of logic circuits has to be aware of the need to test circuits and should be conversant with at least the most basic aspects of testing.
　　Appendix A provides a complete summary of Verilog features. Although use of Verilog is integrated throughout the book, this appendix provides a convenient reference that the reader can'consult from time to time when writing Verilog code.
　　Appendices B, C, and D contain a sequence of tutorials on the MAX+plusII CAD tools.This material is suitable for self-study; it shows the student in a step-by-step manner how to use the CAD software provided with the book.
　　Appendix E gives detailed information about the devices used in illustrative examples.It also includes a brief discussion of TTL technology.
　　WHAT CAN BE COVERED IN A COURSE
　　All the material in the book can be covered in 2 one-quarter courses. A good coverage of the most important material can be achieved in a single one-semester, or even a onequarter, course. This is possible only if the instructor does not spend too much time teaching the intricacies of Verilog and CAD tools. To make this approach possible, we organized the Verilog material in a modular style that is conducive to self-study. Our experience in teaching different classes of students at the University of Toronto shows that the instructor may spend only 2 to 3 lecture hours on Verilog, concentrating mostly on the specification of sequential circuits. The Verilog examples given in the book are largely 'self-explanatory, and students can understand them easily. Moreover, the instructor need not teach how to use the CAD tools, because the MAX+plusH tutorials in Appendices B, C, and D are suitable for self-study.
　　The book is also suitable for a course in logic design that does not include exposure to Verilog. However, some knowledge of Verilog, even at a rudimentary level, is beneficial to the students, and it is a great preparation for a job as a design engineer.
　　One-Semester Course
　　A natural starting point for formal lectures is Chapter 2. The material in Chapter 1 is a general introduction that serves as a motivation for why logic circuits are important and interesting; students can read and understand this material easily.
　　The following material should be covered in lectures:
　　· Chapter 2--all sections.
　　· Chapter 3--sections 3.1 to 3.7. Also, it is useful to cover sections 3.8 and 3.9 if the students have some basic knowledge of electrical circuits.
　　· Chapter 4--sections 4.1 to 4.7 and section 4.12.
　　· Chapter 5--sections 5.1 to 5.5.
　　· Chapter 6--all sections.
　　· Chapter 7--all sections.
　　· Chapter 8--sections 8.1 to 8.9.
　　If time permits, it would also be very useful to cover sections 9.1 to 9.3 and section 9.6 in Chapter 9, as well as one or two examples in Chapter 10.
　　One-Quarter Course
　　 In a one-quarter course the following material can be covered:
　　· Chapter 2--all sections.
　　· Chapter 3--sections 3.1 to 3.3.
　　· Chapter 4--sections 4.1 to 4.5 and section 4.12.
　　· Chapter 5--sections 5.1 to 5.3 and section 5.5.
　　· Chapter 6--all sections.
　　· Chapter 7--sections 7.1 to 7.10 and section 7.13.
　　· Chapter 8--Sections 8.1 to 8.5.
　　A MORE TRADITIONAL APPROACH
　　The material in Chapters 2 and 4 introduces Boolean algebra, combinational logic circuits,and basic minimization techniques. Chapter 2 provides initial exposure to these topics using only AND, OR, NOT, NAND, and NOR gates. Then Chapter 3 discusses the implementation technology details, before proceeding with the synthesis techniques and other types of gates in Chapter 4. The material in Chapter 4 is appreciated better if students understand the technological reasons for the existence of NAND, NOR, and XOR gates, and the various programmable logic devices.
　　An instructor who favors a more traditional approach may cover Chapters 2 and 4 in succession. To understand the use of NAND, NOR, and XOR gates, it is necessary only that the instructor provide a functional definition of these gates.
　　VERILOG
　　Verilog is a complex language, which some instructors feel is too hard for beginning students to grasp. We fully appreciate this issue and have attempted to solve it. It is not necessary to introduce the entire Verilog language. In the book we present the important Verilog constructs that are useful for the design and synthesis of logic circuits. Many other language constructs, such as those that have meaning only when using the language for simulation purposes, are omitted. The Verilog material is introduced gradually, with more advanced features being presented only at points where their use can be demonstrated in the design of relevant circuits.
　　The book includes more than 140 examples of Verilog code. These examples illustrate how Verilog is used to describe a wide range of logic circuits, from those that contain only a few gates to those that represent digital systems such as a simple processor.
　　HOMEWORK PROBLEMS
　　More than 400 homework problems are provided in the book. Solutions to these problems are available to instructors in the Solutions Manual that accompanies the book.
　　LABORATORY
　　The book can be used for a course that does not include laboratory exercises, in which case students can get useful practical experience by simulating the operation of their designed circuits by using the CAD tools provided with the book. If there is an accompanying laboratory, then a number of design examples in the book are suitable for laboratory experiments.Additional experiments are available on the authors' website.
　　ACKNOWLEDGMENTS
　　We wish to express our thanks to the people who have helped during the preparation of the book. Kelly Chan helped with the technical preparation of the manuscript. Dan Vranesic produced a substantial amount of artwork. He and Deshanand Singh also helped with the preparation of the solutions manual. The reviewers, William Barnes, New Jersey Institute of Technology; James Clark, McGill University; Stephen DeWeerth, Georgia Institute of Technology; Clay Gloster, Jr., North Carolina State University (Raleigh); Carl Hamacher,Queen's University; Wei-Ming Lin, University of Texas (Austin); Wayne Loucks, University of Waterloo; Chris Myers, University of Utah; James Palmer, Rochester Institute of Technology; Gandhi Puvvada, University of Southern California; Teodoro Robles, Milwaukee School of Engineering; Tatyana Roziner, Boston University; Rob Rutenbar, Carnegie Mellon University; Charles Silio, Jr., University of Maryland; Scott Smith, University of Missouri (Rolla); Arun Somani, Iowa State University; and Zeljko Zilic, McGill University provided constructive criticism and made numerous suggestions for improvements. We are grateful to the Altera Corporation for providing the MAX+plusII CAD system. The support of McGraw-Hill people has been exemplary. We truly appreciate the help of Kelley Butcher, Catherine Fields Shultz, Michaela Graham, Betsy Jones, Kara Kudrouowicz,Carlise Paulson, Jill Peter, John Wannemacher, and Michelle Whitaker. ...
　　Stephen Brown and Zvonko Vranesic