（已有20条评价）基本信息
- 原书名：Computer Architecture: A Quantitative Approach, Fifth Edition
- 原出版社： Morgan Kaufmann
- 作者： (美)John L. Hennessy David A. Patterson
- 丛书名： 经典原版书库
- 出版社：机械工业出版社
- ISBN：9787111364580
- 上架时间：2012-7-18
- 出版日期：2012 年1月
- 开本：16开
- 页码：856
- 版次：5-1
- 所属分类：计算机 > 计算机组织与体系结构 > 综合
教材
编辑推荐
本书堪称计算机系统结构学科的“圣经”，是计算机设计领域学生和实践者的必读经典。本书系统地介绍了计算机系统的设计基础、存储器层次结构设计、指令级并行及其开发、数据级并行、gpu体系结构、线程级并行和仓库级计算机等。
现今计算机界处于变革之中：移动客户端和云计算正在成为驱动程序设计和硬件创新的主流范型。因此在这个**版中，作者考虑到这个巨大的变化，重点关注了新的平台（个人移动设备和仓库级计算机）和新的体系结构（多核和gpu），不仅介绍了移动计算和云计算等新内容，还讨论了成本、性能、功耗、可靠性等设计要素。每章都有两个真实例子，一个来源于手机，另一个来源于数据中心，以反映计算机界正在发生的革命性变革。
本书内容丰富，既介绍了当今计算机体系结构的**研究成果，也引述了许多计算机系统设计开发方面的实践经验。另外，各章结尾还附有大量的习题和参考文献。本书既可以作为高等院校计算机专业高年级本科生和研究生学习“计算机体系结构”课程的教材或参考书，也可供与计算机相关的专业人士学习参考。
内容简介
书籍
计算机书籍
《计算机体系结构：量化研究方法（英文版.第5版）》堪称计算机系统结构学科的“圣经”，是计算机设计领域学生和实践者的必读经典。本书系统地介绍了计算机系统的设计基础、存储器层次结构设计、指令级并行及其开发、数据级并行、GPU体系结构、线程级并行和仓库级计算机等。
现今计算机界处于变革之中：移动客户端和云计算正在成为驱动程序设计和硬件创新的主流范型。因此在这个最新版中，作者考虑到这个巨大的变化，重点关注了新的平台（个人移动设备和仓库级计算机）和新的体系结构（多核和GPU），不仅介绍了移动计算和云计算等新内容，还讨论了成本、性能、功耗、可靠性等设计要素。每章都有两个真实例子，一个来源于手机，另一个来源于数据中心，以反映计算机界正在发生的革命性变革。
《计算机体系结构：量化研究方法（英文版.第5版）》内容丰富，既介绍了当今计算机体系结构的最新研究成果，也引述了许多计算机系统设计开发方面的实践经验。另外，各章结尾还附有大量的习题和参考文献。本书既可以作为高等院校计算机专业高年级本科生和研究生学习“计算机体系结构”课程的教材或参考书，也可供与计算机相关的专业人士学习参考。
计算机书籍
《计算机体系结构：量化研究方法（英文版.第5版）》堪称计算机系统结构学科的“圣经”，是计算机设计领域学生和实践者的必读经典。本书系统地介绍了计算机系统的设计基础、存储器层次结构设计、指令级并行及其开发、数据级并行、GPU体系结构、线程级并行和仓库级计算机等。
现今计算机界处于变革之中：移动客户端和云计算正在成为驱动程序设计和硬件创新的主流范型。因此在这个最新版中，作者考虑到这个巨大的变化，重点关注了新的平台（个人移动设备和仓库级计算机）和新的体系结构（多核和GPU），不仅介绍了移动计算和云计算等新内容，还讨论了成本、性能、功耗、可靠性等设计要素。每章都有两个真实例子，一个来源于手机，另一个来源于数据中心，以反映计算机界正在发生的革命性变革。
《计算机体系结构：量化研究方法（英文版.第5版）》内容丰富，既介绍了当今计算机体系结构的最新研究成果，也引述了许多计算机系统设计开发方面的实践经验。另外，各章结尾还附有大量的习题和参考文献。本书既可以作为高等院校计算机专业高年级本科生和研究生学习“计算机体系结构”课程的教材或参考书，也可供与计算机相关的专业人士学习参考。
作译者
John L. Hennessy 斯坦福大学校长，IEEE和ACM会士，美国国家工程研究院院士及美国科学艺术研究院院士。Hennessy教授因为在RISC技术方面做出了突出贡献而荣获2001年的Eckert-Mauchly奖章，他也是2001年Seymour Cray计算机工程奖得主，并且和本书另外一位作者David A. Patterson分享了2000年John von Neumann奖。
David A. Patterson 加州大学伯克利分校计算机科学系主任、教授，美国国家工程研究院院士，IEEE和ACM会士，曾因成功的启发式教育方法被IEEE授予James H. Mulligan，Jr.教育奖章。他因为对RISC技术的贡献而荣获1995年IEEE技术成就奖，而在RAID技术方面的成就为他赢得了1999年IEEE Reynold Johnson信息存储奖。2000年他和John L. Hennessy分享了John von Neumann奖。
David A. Patterson 加州大学伯克利分校计算机科学系主任、教授，美国国家工程研究院院士，IEEE和ACM会士，曾因成功的启发式教育方法被IEEE授予James H. Mulligan，Jr.教育奖章。他因为对RISC技术的贡献而荣获1995年IEEE技术成就奖，而在RAID技术方面的成就为他赢得了1999年IEEE Reynold Johnson信息存储奖。2000年他和John L. Hennessy分享了John von Neumann奖。
目录
《计算机体系结构：量化研究方法（英文版.第5版)(计算机系统结构领域的“圣经”)》
Foreword
Preface
Acknowledgments
Chapter 1 Fundamentals of Quantitative Design and Analysis
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Architecture
1.4 Trends in Technology
1.5 Trends in Power and Energy in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance, Price, and Power
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin
Chapter 2 Memory Hierarchy Design
2.1 Introduction
Foreword
Preface
Acknowledgments
Chapter 1 Fundamentals of Quantitative Design and Analysis
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Architecture
1.4 Trends in Technology
1.5 Trends in Power and Energy in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance, Price, and Power
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin
Chapter 2 Memory Hierarchy Design
2.1 Introduction
序言
Why We Wrote This Book
Through five editions of this book, our goal has been to describe the basic princi-ples underlying what will be tomorrow's technological developments. Our excite-ment about the opportunities in computer architecture has not abated, and we echo what we said about the field in the first edition: "It is not a dreary science of paper machines that will never work. No! It's a discipline of keen intellectual interest, requiring the balance of marketplace forces to cost-performance-power,leading to glorious failures and some notable successes."
Our primary objective in writing our first book was to change the way people learn and think about computer architecture. We feel this goal is still valid and important. The field is changing daily and must be studied with real examples and measurements on real computers, rather than simply as a collection of defini-tions and designs that will never need to be realized. We offer an enthusiastic welcome to anyone who came along with us in the past, as well as to those who are joining us now. Either way, we can promise the same quantitative approach to, and analysis of, real systems.
As with earlier versions, we have strived to produce a new edition that will continue to be as relevant for professional engineers and architects as it is for those involved in advanced computer architecture and design courses. Like the first edition, this edition has a sharp focus on new platforms--personal mobile devices and warehouse-scale computers--and new architectures--multicore and GPUs. As much as its predecessors, this edition aims to demystify computer architecture through an emphasis on cost-performance-energy trade-offs and good engineering design. We believe that the field has continued to mature and move toward the rigorous quantitative foundation of long-established scientific and engineering disciplines.
This Edition
We said the fourth edition of Computer Architecture: A Quantitative Approach may have been the most significant since the first edition due to the switch to multicore chips. The feedback we received this time was that the book had lost the sharp focus of the first edition, covering everthing equally but without empha-sis and context. We're pretty sure that won't be said about the fifth edition.
We believe most of the excitement is at the extremes in size of computing,with personal mobile devices (PMDs) such as cell phones and tablets as the cli-ents and warehouse-scale computers offering cloud computing as the server.(Observant readers may seen the hint for cloud computing on the cover.) We are struck by the common theme of these two extremes in cost, performance, and energy efficiency despite their difference in size. As a result, the running context through each chapter is computing for PMDs and for warehouse scale computers,and Chaptett6 is a brand-new chapter on the latter topic.
The other theme is parallelism in all its forms. We first idetify the two types of application-level parallelism in Chapter 1: data-level parallelism (DLP), which arises because there are many data items that can be operated on at the same time,and task-level parallelism (TLP), which arises because tasks of work are created that can operate independently and largely in parallel. We then explain the four architectural styles that exploit DLP and TLP: instruction-level parallelism (ILP) in Chapter 3; vector architectures and graphic processor units (GPUs) in Chapter 4, which is a brand-new chapter for this edition; thread-level parallelism in Chapter 5; and request-level parallelism (RLP) via warehouse-scale computers in Chapter 6, which is also a brand-new chapter for this edition. We moved memory hierarchy earlier in the book to Chapter 2, and we moved the storage systems chapter to Appendix D. We are particularly proud about Chapter 4, which con-tains the most detailed and clearest explanation of GPUs yet, and Chapter 6,which is the first publication of the most recent details of a Google Warehouse-scale computer.
As before, the first three appendices in the book give basics on the MIPS instruction set, memory hierachy, and pipelining for readers who have not read a book like Computer Organization and Design. To keep costs down but still sup-ply supplemental material that are of interest to some readers, available online at http://booksite.mkp.com/9780123838728/are nine more appendices. There are more pages in these appendices than there are in this book!
This edition continues the tradition of using real-world examples to,demon-strate the ideas, and the "Putting It All Together" sections are brand new. The "Putting It All Together" sections of this edition include the pipeline organiza-tions and memory hierarchies of the ARM Cortex A8 processor, the Intel core it processor, the NVIDIA GTX-280 and GTX-480 GPUs, and one of the Google
warehouse-scale computers.
Topic Selection and Organization
As before, we have taken a conservative approach to topic selection, for there are many more interesting ideas in the field than can reasonably be covered in a treat-ment of basic principles. We have steered away from a comprehensive survey of every architecture a reader might encounter. Instead, our presentation focuses on core concepts likely to be found in any new machine. The key criterion remains that of selecting ideas that have been examined and utilized successfully enough to permit their discussion in quantitative terms.
Our intent has always been to focus on material that is not available in equiva-lent form from other sources, so we continue to emphasize advanced content wherever possible. Indeed, there are several systems here whose descriptions cannot be found in the literature. (Readers interested strictly in a more basic introduction to computer architecture should read Computer Organization and Design: The Hardware/Software Interface.)
An Overview of the Content
Chapter 1 has been beefed up in this edition. It includes formulas for energy,static power, dynamic power, integrated circuit costs, reliability, and availability.(These formulas are also found on the front inside cover.) Our hope is that thesetopics can be used through the rest of the book. In addition to the classic quantita-tive principles of computer design and performance measurement, the PIAT sec-tion has been upgraded to use the new SPECPower benchmark.
Our view is that the instruction set architecture is playing less of a role today than in 1990, so we moved this material to Appendix A. It still uses the MIPS64 architecture. (For quick review, a summary of the MIPS ISA can be found on the back inside cover.).For fans of ISAs, Appendix K covers 10 RISC architectures, the 80x86, the DEC VAX, and the IBM 360/370.
We then move onto memory hierarchy in Chapter 2, since it is easy to apply the cost-performance-energy principles to this material and memory is a critical resource for the rest of the chapters. As in the past edition, Appendix B contains an introductory review of cache principles, which is available in case you need it. Chapter 2 discusses 10 advanced optimizations of caches. The chapter includes virtual machines, which offers advantages in protection, software management, and hardware management and play an important role in cloud computing. In addition to covering SRAM and DRAM technologies, the chapter includes new material on Flash memory. The PIAT examples are the ARM Cortex A8, which is used in PMDs, and the Intel Core i7, which is used in servers.
Chapter 3 covers the exploitation of instruction-level parallelism in high- performance processors, including superscalar execution, branch prediction, speculation, dynamic scheduling, and multithreading. As mentioned earlier, Appendix C is a review of pipelining in case you need it. Chapter 3 also sur- veys the limits of ILP. Like Chapter 2, the PIAT examples are again the ARM Cortex A8 and the Intel Core i7. While the third edition contained a great deal on Itanium and VLIW, this material is now in Appendix H, indicating our view that this architecture did not live up to the earlier claims.
The increasing importance of multimedia applications such as games and video
Through five editions of this book, our goal has been to describe the basic princi-ples underlying what will be tomorrow's technological developments. Our excite-ment about the opportunities in computer architecture has not abated, and we echo what we said about the field in the first edition: "It is not a dreary science of paper machines that will never work. No! It's a discipline of keen intellectual interest, requiring the balance of marketplace forces to cost-performance-power,leading to glorious failures and some notable successes."
Our primary objective in writing our first book was to change the way people learn and think about computer architecture. We feel this goal is still valid and important. The field is changing daily and must be studied with real examples and measurements on real computers, rather than simply as a collection of defini-tions and designs that will never need to be realized. We offer an enthusiastic welcome to anyone who came along with us in the past, as well as to those who are joining us now. Either way, we can promise the same quantitative approach to, and analysis of, real systems.
As with earlier versions, we have strived to produce a new edition that will continue to be as relevant for professional engineers and architects as it is for those involved in advanced computer architecture and design courses. Like the first edition, this edition has a sharp focus on new platforms--personal mobile devices and warehouse-scale computers--and new architectures--multicore and GPUs. As much as its predecessors, this edition aims to demystify computer architecture through an emphasis on cost-performance-energy trade-offs and good engineering design. We believe that the field has continued to mature and move toward the rigorous quantitative foundation of long-established scientific and engineering disciplines.
This Edition
We said the fourth edition of Computer Architecture: A Quantitative Approach may have been the most significant since the first edition due to the switch to multicore chips. The feedback we received this time was that the book had lost the sharp focus of the first edition, covering everthing equally but without empha-sis and context. We're pretty sure that won't be said about the fifth edition.
We believe most of the excitement is at the extremes in size of computing,with personal mobile devices (PMDs) such as cell phones and tablets as the cli-ents and warehouse-scale computers offering cloud computing as the server.(Observant readers may seen the hint for cloud computing on the cover.) We are struck by the common theme of these two extremes in cost, performance, and energy efficiency despite their difference in size. As a result, the running context through each chapter is computing for PMDs and for warehouse scale computers,and Chaptett6 is a brand-new chapter on the latter topic.
The other theme is parallelism in all its forms. We first idetify the two types of application-level parallelism in Chapter 1: data-level parallelism (DLP), which arises because there are many data items that can be operated on at the same time,and task-level parallelism (TLP), which arises because tasks of work are created that can operate independently and largely in parallel. We then explain the four architectural styles that exploit DLP and TLP: instruction-level parallelism (ILP) in Chapter 3; vector architectures and graphic processor units (GPUs) in Chapter 4, which is a brand-new chapter for this edition; thread-level parallelism in Chapter 5; and request-level parallelism (RLP) via warehouse-scale computers in Chapter 6, which is also a brand-new chapter for this edition. We moved memory hierarchy earlier in the book to Chapter 2, and we moved the storage systems chapter to Appendix D. We are particularly proud about Chapter 4, which con-tains the most detailed and clearest explanation of GPUs yet, and Chapter 6,which is the first publication of the most recent details of a Google Warehouse-scale computer.
As before, the first three appendices in the book give basics on the MIPS instruction set, memory hierachy, and pipelining for readers who have not read a book like Computer Organization and Design. To keep costs down but still sup-ply supplemental material that are of interest to some readers, available online at http://booksite.mkp.com/9780123838728/are nine more appendices. There are more pages in these appendices than there are in this book!
This edition continues the tradition of using real-world examples to,demon-strate the ideas, and the "Putting It All Together" sections are brand new. The "Putting It All Together" sections of this edition include the pipeline organiza-tions and memory hierarchies of the ARM Cortex A8 processor, the Intel core it processor, the NVIDIA GTX-280 and GTX-480 GPUs, and one of the Google
warehouse-scale computers.
Topic Selection and Organization
As before, we have taken a conservative approach to topic selection, for there are many more interesting ideas in the field than can reasonably be covered in a treat-ment of basic principles. We have steered away from a comprehensive survey of every architecture a reader might encounter. Instead, our presentation focuses on core concepts likely to be found in any new machine. The key criterion remains that of selecting ideas that have been examined and utilized successfully enough to permit their discussion in quantitative terms.
Our intent has always been to focus on material that is not available in equiva-lent form from other sources, so we continue to emphasize advanced content wherever possible. Indeed, there are several systems here whose descriptions cannot be found in the literature. (Readers interested strictly in a more basic introduction to computer architecture should read Computer Organization and Design: The Hardware/Software Interface.)
An Overview of the Content
Chapter 1 has been beefed up in this edition. It includes formulas for energy,static power, dynamic power, integrated circuit costs, reliability, and availability.(These formulas are also found on the front inside cover.) Our hope is that thesetopics can be used through the rest of the book. In addition to the classic quantita-tive principles of computer design and performance measurement, the PIAT sec-tion has been upgraded to use the new SPECPower benchmark.
Our view is that the instruction set architecture is playing less of a role today than in 1990, so we moved this material to Appendix A. It still uses the MIPS64 architecture. (For quick review, a summary of the MIPS ISA can be found on the back inside cover.).For fans of ISAs, Appendix K covers 10 RISC architectures, the 80x86, the DEC VAX, and the IBM 360/370.
We then move onto memory hierarchy in Chapter 2, since it is easy to apply the cost-performance-energy principles to this material and memory is a critical resource for the rest of the chapters. As in the past edition, Appendix B contains an introductory review of cache principles, which is available in case you need it. Chapter 2 discusses 10 advanced optimizations of caches. The chapter includes virtual machines, which offers advantages in protection, software management, and hardware management and play an important role in cloud computing. In addition to covering SRAM and DRAM technologies, the chapter includes new material on Flash memory. The PIAT examples are the ARM Cortex A8, which is used in PMDs, and the Intel Core i7, which is used in servers.
Chapter 3 covers the exploitation of instruction-level parallelism in high- performance processors, including superscalar execution, branch prediction, speculation, dynamic scheduling, and multithreading. As mentioned earlier, Appendix C is a review of pipelining in case you need it. Chapter 3 also sur- veys the limits of ILP. Like Chapter 2, the PIAT examples are again the ARM Cortex A8 and the Intel Core i7. While the third edition contained a great deal on Itanium and VLIW, this material is now in Appendix H, indicating our view that this architecture did not live up to the earlier claims.
The increasing importance of multimedia applications such as games and video
媒体评论
“本书之所以成为永恒的经典，是因为它的每一次再版都不仅仅是更新补充，而是一次全面的修订，对这个激动人心且快速变化领域给出了最及时的信息和最独到的解读。对于我来说,即使已有二十多年的从业经历，再次阅读本书仍自觉学无止境,感佩于两位卓越大师的渊博学识和深厚功底。”
——Luiz Andre Barroso，Google公司
——Luiz Andre Barroso，Google公司
书摘
The pressure of both a fast clock cycle and power limitations encourages limited size for first-level caches. Similarly， use of lower levels of associativity can reduce both hit time and power， although such trade-offs are more complex than those involving size.
The critical timing path in a cache hit is the three-step process of addressing the tag memory using the index portion of the address， comparing the read tag value to the address， and setting the multiplexor to choose the correct data item if the cache is set associative. Direct-mapped caches can overlap the tag check with the transmission of the data， effectively reducing hit time. Furthermore， lower levels of associativity will usually reduce power because fewer cache lines must be accessed.
Although the total amount of on-chip cache has increased dramatically with new generations of microprocessors， due to the clock rate impact arising from a larger L1 cache， the size of the L1 caches has recently increased either slightly or not at all. In many recent processors， designers have opted for more associativity rather than larger caches. An additional consideration in choosing the associativity is the possibility of eliminating address aliases; we discuss this shortly.
One approach to determining the impact on hit time and power consumption in advance of building a chip is to use CAD tools. CACTI is a program to estimate the access time and energy consumption of alternative cache structures on CMOS microprocessors within 10% of more detailed CAD tools. For a given minimum feature size， CACTI estimates the hit time of caches as cache size varies， associativity， number of read/write ports， and more complex parameters. Figure 2.3 shows the estimated impact on hit time as cache size and associativity are varied.
……
The critical timing path in a cache hit is the three-step process of addressing the tag memory using the index portion of the address， comparing the read tag value to the address， and setting the multiplexor to choose the correct data item if the cache is set associative. Direct-mapped caches can overlap the tag check with the transmission of the data， effectively reducing hit time. Furthermore， lower levels of associativity will usually reduce power because fewer cache lines must be accessed.
Although the total amount of on-chip cache has increased dramatically with new generations of microprocessors， due to the clock rate impact arising from a larger L1 cache， the size of the L1 caches has recently increased either slightly or not at all. In many recent processors， designers have opted for more associativity rather than larger caches. An additional consideration in choosing the associativity is the possibility of eliminating address aliases; we discuss this shortly.
One approach to determining the impact on hit time and power consumption in advance of building a chip is to use CAD tools. CACTI is a program to estimate the access time and energy consumption of alternative cache structures on CMOS microprocessors within 10% of more detailed CAD tools. For a given minimum feature size， CACTI estimates the hit time of caches as cache size varies， associativity， number of read/write ports， and more complex parameters. Figure 2.3 shows the estimated impact on hit time as cache size and associativity are varied.
……
