计算机体系结构：量化研究方法(英文版.第5版)(计算机系统结构领域的“圣经”)

.2.2 ten advanced optimizations of cache performance
2.3 memory technology and optimizations
2.4 protection: virtual memory and virtual machines
2.5 crosscutting issues: the design of memory hierarchies
2.6 putting it all together: memory hierachies in the arm cortex-as and intel core i7
2.7 fallacies and pitfalls
2.8 concluding remarks: looking ahead
2.9 historical perspective and references case studies and exercises by norman p. jouppi, naveen muralimanohar, and sheng li
chapter 3 nstruction-level parallelism and its exploitation
3.1 instruction-level parallelism: concepts and challenges
3.2 basic compiler techniques for exposing ilp
3.3 reducing branch costs with advanced branch prediction
3.4 overcoming data hazards with dynamic scheduling
3.5 dynamic scheduling: examples and the algorithm
3.6 hardware-based speculation
3.7 exploiting ilp using multiple issue and static scheduling
3.8 exploiting ilp using dynamic scheduling, multiple issue, and speculation
3.9 advanced techniques for instruction delivery and speculation
3.10 studies of the limitations ofllp
3.11 cross-cutting issues: ilp approaches and the memory system
3.12 multithreading: exploiting thread-level parallelism to improve uniprocessor throughput
3.13 putting it all together: the intel core i7 and arm cortex-as
3.14 fallacies and pitfalls
3.15 concluding remarks: what's ahead?
3.16 historical perspective and references case studies and exercises by jason d. bakos and robert r colwell
chapter4 data-level parallelism in vector, simd, and gpu architectures
4.1 introduction
4.2 vector architecture
4.3 simd instruction set extensions for multimedia
4.4 graphics processing units
4.5 detecting and enhancing loop-level parallelism
4.6 crosscutting issues
4.7 putting it all together: mobile versus server gpus and tesla versus core i7
4.8 fallacies and pitfalls
4.9 concluding remarks
4.10 historical perspective and references case study and exercises by jason d. bakos
chapter 5 thread-level parallelism
5.1 introduction
5.2 centralized shared-memory architectures
5.3 performance of symmetric shared-memory multiprocessors
5.4 distributed shared-memory and directory-based coherence
5.5 synchronization: the basics
5.6 models of memory consistency: an introduction
5.7 crosscutting issues
5.8 putting it all together: multicore processors and their performance
5.9 fallacies and pitfalls
5.10 concluding remarks
5.11 historical perspectives and references
case studies and exercises by amr zaky and david a. wood
chapter 6 warehouse-scale computers to exploit request-level and
data-level parallelism
6.1 introduction
6.2 programming models and'workloads for warehouse-scale computers
6.3 computer architecture of warehouse-scale computers
6.4 physical infrastructure and costs of warehouse-scale computers
6.5 cloud computing: the return of utility computing
6.6 crosscutting issues
6.7 putting it all together: a google warehouse-scale computer
6.8 fallacies and pitfalls
6.9 concluding remarks
6.10 historical perspectives and references
case studies and exercises by parthasarathy ranganathan
appendix a instruction set principles
a.1 introduction
a.2 classifying instruction set architectures
a.3 memory addressing
a.4 type and size of operands
a.s operations in the instruction set
a.6 instructions for control flow
a.7 encoding an instruction set
a.8 crosscutting issues: the role of compilers
a.9 putting it all together: the mips architecture
a.10 fallacies and pitfalls
a.11 concluding remarks
a.12 historical perspective and references
exercises by gregory d. peterson
appendix b review of memory hierarchy
b.1 introduction
b.2 cache performance
b.3 six basic cache optimizations
b.4 virtual memory
b.5 protection and examples of virtual memory
b.6 fallacies and pitfalls
b.7 concluding remarks
b.8 historical perspective and references
exercises by amr zaky
appendix c pipelining: basic and intermediate concepts
c.1 introduction
c.2 the major hurdle of pipelining--pipeline hazards
c.3 how is pipelining implemented?
c,4 what makes pipelining hard to implement?
c.5 extending the mips pipeline to handle multicycle operations
c.6 putting it all together: the mips r4000 pipeline
c.7 crosscutting issues
c.8 fallacies and pitfalls
c.9 concluding remarks
c.10 historical perspective and references
updated exercises by diana franklin
online appendices
appendix d storage systems
appendix e embedded systems
by thomasm conte
appendix f interconnection networks
revised by timothy m. pinkston ond jose duoto
appendix g vector processors in more depth
revised by krste asonovic
appendix h hardware and software for vliw and epic
appendix i large-scale multiprocessors and scientific applications
appendix j computer arithmetic
by david goldberg
appendix k survey of instruction set architectures
appendix l historical perspectives and references
references
index
1.1 introduction
1.2 classes of computers
1.3 defining computer architecture
1.4 trends in technology
1.5 trends in power and energy in integrated circuits
1.6 trends in cost
1.7 dependability
1.8 measuring reporting, and summarizing performance
1.9 quantitative principles of computer design
1.10 putting it all together: performance, price, and power
1.11 fallacies and pitfalls
1.12 concluding remarks
1.13 historical perspectives and references
1.14 case studies and exercises by diana franklin

.　　processing has also increased the importance of achitectures that can exploit data-level parallelism. In particular, there is a rising interest in computing using graphi-cal processing units (GPUs), yet few architects understand how GPUs really work.We decided to write a new chapter in large part to unveil this new style of com-puter architecture. Chapter 4 starts with an introduction to vector architectures,which acts as a foundation on which to build explanations of multimedia SIMD instrution set extensions and GPUs. (Appendix G goes into even more depth on vector architecliures.) The section on GPUs was the most difficult to write in this book, in that it took many iterations to get an accurate description that was also easy to understand. A significant challenge was the terminology. We decided to go with our own terms and then provide a translation between our terms and the offi-cial NVIDIA terms. (A copy of that table can be found in the back inside cover pages.) This chapter introduces the Roofline performance model and then uses it to compare the intel Core i7 and the NVIDIA GTX 280 and GTX 480 GPUs. The chapter also describes the Tegra 2 GPU for PMDs.
　　Chapter 5 describes multicore processors. It explores symmetric and distributed-memory architectures, examining both organizational principles and performance. Topics in synchronization and memory consistency models are next. The example is the Intel Core i7. Readers interested in interconnection net-works on a chip should read Appendix F, and those interested in larger scale mul-tiprocessors and scientific applications should read Appendix I.
　　As mentioned earlier, Chapter 6 describes the newest topic in computer archi-tecture, warehouse-scale computers (WSCs). Based on help from engineers at Amazon Web Services and Google, this chapter integrates details on design, cost,and performance of WSCs that few architects are aware of. It starts with the pop-ular MapReduce programming model before describing the architecture and physical implemention of WSCs, including cost. The costs allow us to explain the emergence of cloud computing, whereby it can be cheaper to compute using WSCs in the cloud than in your local datacenter. The PIAT example is a descrip-tion of a Google WSC that includes information published for the first time in this book.
　　This brings us to Appendices A through L. Appendix A covers principles of ISAs, including MIPS64, and Appendix K describes 64-bit versions of Alpha,MIPS, PowerPC, and SPARC and their multimedia extensions. It also includes some classic architectures (80x86, VAX, and IBM 360/370) and popular embedded instruction sets (ARM, Thumb, SuperH, MIPS 16, and Mitsubishi M32R). Appen-dix H is related, in that it covers architectures and compilers for VLIW ISAs.As mentioned earlier, Appendices B and C are tutorials on basic caching andpipelining concepts. Readers relatively new to caching should read Appendix B before Chapter 2 and those new to pipelining should read Appendix C before Chapter 3.
　　Appendix D, "Storage Systems," has an expanded discussion of reliability and availability, a tutorial on RAID with a description of RAID 6 schemes, and rarely found failure statistics of real systems. It continues to provide an introduction to queuing theory and I/O performance benchmarks. We evaluate the cost, perfor-mance, and reliability of a real cluster: the Internet Archive. The "Putting It All Together" example is the NetApp FAS6000 filer.
　　Appendix E, by Thomas M. Conte, consolidates the embedded material in one place.
　　Appendix F, on interconnection networks, has been revised by Timothy M.Pinkston and Jose Duato. Appendix G written originally by Krste Asanovic, includes a description of vector processors. We thirik these two appendices are some of the best material we know of on each topic.
　　Appendix H describes VLIW and EPIC, the architecture of Itanium.
　　Appendix I describes parallel processing applications and coherence protocols for larger-scale, shared-memory multiprocessing. Appendix J, by David Gold-berg, describes computer arithmetic.
　　 Appendix L collects the "Historical Perspective and References" from each
　　chapter into a single appendix. It attempts to give proper credit for the ideas in each chapter and a sense of the history surrounding the inventions. We like to think of this as presenting the human drama of computer design. It also supplies references that the student of architecture may want to pursue. If you have time,we recommend reading some of the classic papers in the field that are mentioned in these sections. It is both enjoyable and educational to hear the ideas directly from the creators. "Historical Perspective" was one of the most popular sections of prior editions.
　　 Navigating the Text
　　 There is no single best order in which to approach these chapters and appendices,except that all readers should start with Chapter 1. If you don't want to read everything, here are some suggested sequences:
　　· Memory Hierarchy: Appendix B, Chapter 2, and Appendix D.
　　· Instruction-Level Parallelism: Appendix C, Chapter 3, and Appendix H
　　· Data-Level Parallelism: Chapters 4 and 6, Appendix G
　　· Thread-Level Parallelism: Chapter 5, Appendices F and I
　　· Request-Level Parallelism: Chapter 6
　　· ISA: Appendices A and K
　　Appendix E can be read at any time, but it might work best if read after the ISA and cache sequences. Appendix J can be read whenever arithmetic moves you.You should read the corresponding portion of Appendix L after you complete each chapter.
　　Chapter Structure
　　The material we have selected has been stretched upon a consistent framework that is followed in each chapter. We start by explaining the ideas of a chapter.These ideas are followed by a "Crosscutting Issues" section, a feature that shows how the ideas covered in one chapter interact with those given in other chapters.This is followed by a "Putting It All Together" section that ties these ideas together by showing how they are used in a real machine.
　　Next in the sequence is "Fallacies and Pitfalls," which lets readers learn from the mistakes of others. We show examples of common misunderstandings and architectural traps that are difficult to avoid even when you know they are lying in wait for you. The "Fallacies and Pitfalls" sections is one of the most popular sections of the book. Each chapter ends with a "Concluding Remarks" section.
　　Case Studies with Exercises
　　Each chapter ends with case studies and accompanying exercises. Authored by experts in industry and academia, the case studies explore key chapter concepts and verify understanding through increasingly challenging exercises. Instructors should find the case studies sufficiently detailed and robust to allow them to cre-ate their own additional exercises.
　　 Brackets for each exercise ([chapter. section]) indicate the text sections of pti-mary relevance to completing the exercise. We hope this helps readers to avoid exercises for which they haven't read the corresponding section, in addition to providing the source for review. Exercises are rated, to give the reader a sense of the amount of time required to complete an exercise:
　　[10] Less than 5 minutes (to read and understand)
　　[15] 5-15 minutes for a full answer
　　[20] 15-20 minutes for a full answer
　　[25] 1 hour for a full written answer
　　[30] Short programming project: less than I full day of programming
　　[40] Significant programming project: 2 weeks of elapsed time
　　[Discussion] Topic for discussion with others
　　Solutions to the case studies and exercises are available for instructors who register at textbooks, elsevier, com.
　　Supplemental Materials
　　A variety of resources are available online at http://booksite,mkp.com/9780123838728/,
　　including the following:
　　·Reference appendices--some guest authored by subject experts--coveting a range of advanced topics
　　·Historical Perspectives material that explores the development of the key ideas presented in each of the chapters in the text
　　·Instructor slides in PowerPoint
　　·Figures from the book in PDF, EPS, and PPT formats
　　·Links to related material on the Web
　　·List of errata
　　New materials and links to other resources available on the Web will be added on a regular basis.
　　Helping Improve This Book
　　Finally, it is possible to make money while reading this book. (Talk about cost-performance!) If you read the Acknowledgments that follow, you will see that we went to great lengths to correct mistakes. Since a book goes through many print-ings, we have the opportunity to make even more corrections. If you uncover any remaining resilient bugs, please contact the publisher by electronic mail (ca5bugs@mkp.com)
　　We welcome general comments to the text and invite you to send them to a separate email address at ca5comments@mkp, com.
　　Concluding Remarks
　　Once again this book is a true co-authorship, with each of us writing half the chapters and an equal share of the appendices. We can't imagine how long it would have taken without someone else doing half the work, offering inspiration when the task seemed hopeless, providing the key insight to explain a difficult concept, supplying reviews over the weekend of chapters, and commiserating when the weight of our other obligations made it hard to pick up the pen. (These obligations have escalated exponentially with the number of editions, as the biog-raphies attest.) Thus, once again we share equally the blame for what you are about to read.
　　John Hennessy : David Patterson