数字集成电路设计：从VLSI体系结构到CMOS制造：英文

.chapter 2 from algorithms to architectures 44
2.1 the goals of architecture design 44
2.1.1 agenda 45
2.2 the architectural antipodes 45
2.2.1 what makes an algorithm suitable for a dedicated vlsi architecture? 50
2.2.2 there is plenty of land between the architectural antipodes 53
2.2.3 assemblies of general-purpose and dedicated processing units 54
2.2.4 coprocessors 55
2.2.5 application-specific instruction set processors 55
2.2.6 configurable computing 58
2.2.7 extendable instruction set processors 59
2.2.8 digest 60
2.3 a transform approach to vlsi architecture design 61
2.3.1 there is room for remodelling in the algorithmic domain 62
2.3.2 . . . and there is room in the architectural domain 64
2.3.3 systems engineers and vlsi designers must collaborate 64
2.3.4 a graph-based formalism for describing processing algorithms 65
2.3.5 the isomorphic architecture 66
2.3.6 relative merits of architectural alternatives 67
2.3.7 computation cycle versus clock period 69
2.4 equivalence transforms for combinational computations 70
2.4.1 common assumptions 71
2.4.2 iterative decomposition 72
2.4.3 pipelining 75
2.4.4 replication 79
2.4.5 time sharing 81
2.4.6 associativity transform 86
2.4.7 other algebraic transforms 87
2.4.8 digest 87
2.5 options for temporary storage of data 89
2.5.1 data access patterns 89
2.5.2 available memory configurations and area occupation 89
2.5.3 storage capacities 90
2.5.4 wiring and the costs of going off-chip 91
2.5.5 latency and timing 91
2.5.6 digest 92
2.6 equivalence transforms for nonrecursive computations 93
2.6.1 retiming 94
2.6.2 pipelining revisited 95
2.6.3 systolic conversion 97
2.6.4 iterative decomposition and time-sharing revisited 98
2.6.5 replication revisited 98
2.6.6 digest 99
2.7 equivalence transforms for recursive computations 99
2.7.1 the feedback bottleneck 100
2.7.2 unfolding of first-order loops 101
2.7.3 higher-order loops 103
2.7.4 time-variant loops 105
2.7.5 nonlinear or general loops 106
2.7.6 pipeline interleaving is not an equivalence transform 109
2.7.7 digest 111
2.8 generalizations of the transform approach 112
2.8.1 generalization to other levels of detail 112
2.8.2 bit-serial architectures 113
2.8.3 distributed arithmetic 116
2.8.4 generalization to other algebraic structures 118
2.8.5 digest 121
2.9 conclusions 122
2.9.1 summary 122
2.9.2 the grand architectural alternatives from an energy point of view 124
2.9.3 a guide to evaluating architectural alternatives 126
2.10 problems 128
2.11 appendix i: a brief glossary of algebraic structures 130
2.12 appendix ii: area and delay figures of vlsi subfunctions 133
chapter 3 functional verification 136
3.1 how to establish valid functional specifications 137
3.1.1 formal specification 138
3.1.2 rapid prototyping 138
3.2 developing an adequate simulation strategy 139
3.2.1 what does it take to uncover a design flaw during simulation? 139
3.2.2 stimulation and response checking must occur automatically 140
3.2.3 exhaustive verification remains an elusive goal 142
3.2.4 all partial verification techniques have their pitfalls 143
3.2.5 collecting test cases from multiple sources helps 150
3.2.6 assertion-based verification helps 150
3.2.7 separating test development from circuit design helps 151
3.2.8 virtual prototypes help to generate expected responses 153
3.3 reusing the same functional gauge throughout the entire design cycle 153
3.3.1 alternative ways to handle stimuli and expected responses 155
3.3.2 modular testbench design 156
3.3.3 a well-defined schedule for stimuli and responses 156
3.3.4 trimming run times by skipping redundant simulation sequences 159
3.3.5 abstracting to higher-level transactions on higher-level data 160
3.3.6 absorbing latency variations across multiple circuit models 164
3.4 conclusions 166
3.5 problems 168
3.6 appendix i: formal approaches to functional verification 170
3.7 appendix ii: deriving a coherent schedule for simulation and test 171
chapter 4 modelling hardware with vhdl 175
4.1 motivation 175
4.1.1 why hardware synthesis? 175
4.1.2 what are the alternatives to vhdl? 176
4.1.3 what are the origins and aspirations of the ieee 1076 standard? 176
4.1.4 why bother learning hardware description languages? 179
4.1.5 agenda 180
4.2 key concepts and constructs of vhdl 180
4.2.1 circuit hierarchy and connectivity 181
4.2.2 concurrent processes and process interaction 185
4.2.3 a discrete replacement for electrical signals 192
4.2.4 an event-based concept of time for governing simulation 200
4.2.5 facilities for model parametrization 211
4.2.6 concepts borrowed from programming languages 216
4.3 putting vhdl to service for hardware synthesis 223
4.3.1 synthesis overview 223
4.3.2 data types 224
4.3.3 registers, finite state machines, and other sequential subcircuits 225
4.3.4 rams, roms, and other macrocells 231
4.3.5 circuits that must be controlled at the netlist level 233
4.3.6 timing constraints 234
4.3.7 limitations and caveats for synthesis 238
4.3.8 how to establish a register transfer-level model step by step 238
4.4 putting vhdl to service for hardware simulation 242
4.4.1 ingredients of digital simulation 242
4.4.2 anatomy of a generic testbench 242
4.4.3 adapting to a design problem at hand 245
4.4.4 the vital modelling standard ieee 1076.4 245
4.5 conclusions 247
4.6 problems 248
4.7 appendix i: books and web pages on vhdl 250
4.8 appendix ii: related extensions and standards 251
4.8.1 protected shared variables ieee 1076a 251
4.8.2 the analog and mixed-signal extension ieee 1076.1 252
4.8.3 mathematical packages for real and complex numbers ieee 1076.2 253
4.8.4 the arithmetic packages ieee 1076.3 254
4.8.5 a language subset earmarked for synthesis ieee 1076.6 254
4.8.6 the standard delay format (sdf) ieee 1497 254
4.8.7 a handy compilation of type conversion functions 255
4.9 appendix iii: examples of vhdl models 256
4.9.1 combinational circuit models 256
4.9.2 mealy, moore, and medvedev machines 261
4.9.3 state reduction and state encoding 268
4.9.4 simulation testbenches 270
4.9.5 working with vhdl tools from different vendors 285
chapter 5 the case for synchronous design 286
5.1 introduction 286
5.2 the grand alternatives for regulating state changes 287
5.2.1 synchronous clocking 287
5.2.2 asynchronous clocking 288
5.2.3 self-timed clocking 288
5.3 why a rigorous approach to clocking is essential in vlsi 290
5.3.1 the perils of hazards 290
5.3.2 the pros and cons of synchronous clocking 291
5.3.3 clock-as-clock-can is not an option in vlsi 293
5.3.4 fully self-timed clocking is not normally an option either 294
5.3.5 hybrid approaches to system clocking 294
5.4 the dos and don’ts of synchronous circuit design 296
5.4.1 first guiding principle: dissociate signal classes! 296
5.4.2 second guiding principle: allow circuits to settle before clocking! 298
5.4.3 synchronous design rules at a more detailed level 298
5.5 conclusions 306
5.6 problems 306
5.7 appendix: on identifying signals 307
5.7.1 signal class 307
5.7.2 active level 308
5.7.3 signaling waveforms 309
5.7.4 three-state capability 311
5.7.5 inputs, outputs, and bidirectional terminals 311
5.7.6 present state vs. next state 312
5.7.7 syntactical conventions 312
5.7.8 a note on upper- and lower-case letters in vhdl 313
5.7.9 a note on the portability of names across eda platforms 314
chapter 6 clocking of synchronous circuits 315
6.1 what is the difficulty in clock distribution? 315
6.1.1 agenda 316
6.1.2 timing quantities related to clock distribution 317
6.2 how much skew and jitter does a circuit tolerate? 317
6.2.1 basics 317
6.2.2 single-edge-triggered one-phase clocking 319
6.2.3 dual-edge-triggered one-phase clocking 326
6.2.4 symmetric level-sensitive two-phase clocking 327
6.2.5 unsymmetric level-sensitive two-phase clocking 331
6.2.6 single-wire level-sensitive two-phase clocking 334
6.2.7 level-sensitive one-phase clocking and wave pipelining 336
6.3 how to keep clock skew within tight bounds 339
6.3.1 clock waveforms 339
6.3.2 collective clock buffers 340
6.3.3 distributed clock buffer trees 343
6.3.4 hybrid clock distribution networks 344
6.3.5 clock skew analysis 345
6.4 how to achieve friendly input/output timing 346
6.4.1 friendly as opposed to unfriendly i/o timing 346
6.4.2 impact of clock distribution delay on i/o timing 347
6.4.3 impact of ptv variations on i/o timing 349
6.4.4 registered inputs and outputs 350
6.4.5 adding artificial contamination delay to data inputs 350
6.4.6 driving input registers from an early clock 351
6.4.7 tapping a domain’s clock from the slowest component therein 351
6.4.8 “zero-delay” clock distribution by way of a dll or pll 352
6.5 how to implement clock gating properly 353
6.5.1 traditional feedback-type registers with enable 353
6.5.2 a crude and unsafe approach to clock gating 354
6.5.3 a simple clock gating scheme that may work under certain conditions 355
6.5.4 safe clock gating schemes 355
6.6 summary 357
6.7 problems 361
chapter 7 acquisition of asynchronous data 364
7.1 motivation 364
7.2 the data consistency problem of vectored acquisition 366
7.2.1 plain bit-parallel synchronization 366
7.2.2 unit-distance coding 367
7.2.3 suppression of crossover patterns 368
7.2.4 handshaking 369
7.2.5 partial handshaking 371
7.3 the data consistency problem of scalar acquisition 373
7.3.1 no synchronization whatsoever 373
7.3.2 synchronization at multiple places 373
7.3.3 synchronization at a single place 373
7.3.4 synchronization from a slow clock 374
7.4 metastable synchronizer behavior 374
7.4.1 marginal triggering and how it becomes manifest 374
7.4.2 repercussions on circuit functioning 378
7.4.3 a statistical model for estimating synchronizer reliability 379
7.4.4 plesiochronous interfaces 381
7.4.5 containment of metastable behavior 381
7.5 summary 384
7.6 problems 384
chapter 8 gate- and transistor-level design 386
8.1 cmos logic gates 386
8.1.1 the mosfet as a switch 387
8.1.2 the inverter 388
8.1.3 simple cmos gates 396
8.1.4 composite or complex gates 399
8.1.5 gates with high-impedance capabilities 403
8.1.6 parity gates 406
8.1.7 adder slices 407
8.2 cmos bistables 409
8.2.1 latches 410
8.2.2 function latches 412
8.2.3 single-edge-triggered flip-flops 413
8.2.4 the mother of all flip-flops 415
8.2.5 dual-edge-triggered flip-flops 417
8.2.6 digest 418
8.3 cmos on-chip memories 418
8.3.1 static ram 418
8.3.2 dynamic ram 423
8.3.3 other differences and commonalities 424
8.4 electrical cmos contraptions 425
8.4.1 snapper 425
8.4.2 schmitt trigger 426
8.4.3 tie-off cells 427
8.4.4 filler cell or fillcap 428
8.4.5 level shifters and input/output buffers 429
8.4.6 digitally adjustable delay lines 429
8.5 pitfalls 430
8.5.1 busses and three-state nodes 430
8.5.2 transmission gates and other bidirectional components 434
8.5.3 what do we mean by safe design? 437
8.5.4 microprocessor interface circuits 438
8.5.5 mechanical contacts 440
8.5.6 conclusions 440
8.6 problems 442
8.7 appendix i: summary on electrical mosfet models 445
8.7.1 naming and counting conventions 445
8.7.2 the sah model 446
8.7.3 the shichman–hodges model 450
8.7.4 the alpha-power-law model 450
8.7.5 second-order effects 452
8.7.6 effects not normally captured by transistor models 455
8.7.7 conclusions 456
8.8 appendix ii: the bipolar junction transistor 457
chapter 9 energy efficiency and heat removal 459
9.1 what does energy get dissipated for in cmos circuits? 459
9.1.1 charging and discharging of capacitive loads 460
9.1.2 crossover currents 465
9.1.3 resistive loads 467
9.1.4 leakage currents 468
9.1.5 total energy dissipation 470
9.1.6 cmos voltage scaling 471
9.2 how to improve energy efficiency 474
9.2.1 general guidelines 474
9.2.2 how to reduce dynamic dissipation 476
9.2.3 how to counteract leakage 482
9.3 heat flow and heat removal 488
9.4 appendix i: contributions to node capacitance 490
9.5 appendix ii: unorthodox approaches 491
9.5.1 subthreshold logic 491
9.5.2 voltage-swing-reduction techniques 492
9.5.3 adiabatic logic 492
chapter 10 signal integrity 495
10.1 introduction 495
10.1.1 how does noise enter electronic circuits? 495
10.1.2 how does noise affect digital circuits? 496
10.1.3 agenda 499
10.2 crosstalk 499
10.3 ground bounce and supply droop 499
10.3.1 coupling mechanisms due to common series impedances 499
10.3.2 where do large switching currents originate? 501
10.3.3 how severe is the impact of ground bounce? 501
10.4 how to mitigate ground bounce 504
10.4.1 reduce effective series impedances 505
10.4.2 separate polluters from potential victims 510
10.4.3 avoid excessive switching currents 513
10.4.4 safeguard noise margins 517
10.5 conclusions 519
10.6 problems 519
10.7 appendix: derivation of second-order approximation 521
chapter 11 physical design 523
11.1 agenda 523
11.2 conducting layers and their characteristics 523
11.2.1 geometric properties and layout rules 523
11.2.2 electrical properties 527
11.2.3 connecting between layers 527
11.2.4 typical roles of conducting layers 529
11.3 cell-based back-end design 531
11.3.1 floorplanning 531
11.3.2 identify major building blocks and clock domains 532
11.3.3 establish a pin budget 533
11.3.4 find a relative arrangement of all major building blocks 534
11.3.5 plan power, clock, and signal distribution 535
11.3.6 place and route (p&r) 538
11.3.7 chip assembly 539
11.4 packaging 540
11.4.1 wafer sorting 543
11.4.2 wafer testing 543
11.4.3 backgrinding and singulation 544
11.4.4 encapsulation 544
11.4.5 final testing and binning 544
11.4.6 bonding diagram and bonding rules 545
11.4.7 advanced packaging techniques 546
11.4.8 selecting a packaging technique 551
11.5 layout at the detail level 551
11.5.1 objectives of manual layout design 552
11.5.2 layout design is no wysiwyg business 552
11.5.3 standard cell layout 556
11.5.4 sea-of-gates macro layout 559
11.5.5 sram cell layout 559
11.5.6 lithography-friendly layouts help improve fabrication yield 561
11.5.7 the mesh, a highly efficient and popular layout arrangement 562
11.6 preventing electrical overstress 562
11.6.1 electromigration 562
11.6.2 electrostatic discharge 565
11.6.3 latch-up 571
11.7 problems 575
11.8 appendix i: geometric quantities advertized in vlsi 576
11.9 appendix ii: on coding diffusion areas in layout drawings 577
11.10 appendix iii: sheet resistance 579
chapter 12 design verification 581
12.1 uncovering timing problems 581
12.1.1 what does simulation tell us about timing problems? 581
12.1.2 how does timing verification help? 585
12.2 how accurate are timing data? 587
12.2.1 cell delays 588
12.2.2 interconnect delays and layout parasitics 593
12.2.3 making realistic assumptions is the point 597
12.3 more static verification techniques 598
12.3.1 electrical rule check 598
12.3.2 code inspection 599
12.4 post-layout design verification 601
12.4.1 design rule check 602
12.4.2 manufacturability analysis 604
12.4.3 layout extraction 605
12.4.4 layout versus schematic 605
12.4.5 equivalence checking 606
12.4.6 post-layout timing verification 606
12.4.7 power grid analysis 607
12.4.8 signal integrity analysis 607
12.4.9 post-layout simulations 607
12.4.10 the overall picture 607
12.5 conclusions 608
12.6 problems 609
12.7 appendix i: cell and library characterization 611
12.8 appendix ii: equivalent circuits for interconnect modelling 612
chapter 13 vlsi economics and project management 615
13.1 agenda 615
13.2 models of industrial cooperation 617
13.2.1 systems assembled from standard parts exclusively 617
13.2.2 systems built around program-controlled processors 618
13.2.3 systems designed on the basis of field-programmable logic 619
13.2.4 systems designed on the basis of semi-custom asics 620
13.2.5 systems designed on the basis of full-custom asics 622
13.3 interfacing within the asic industry 623
13.3.1 handoff points for ic design data 623
13.3.2 scopes of ic manufacturing services 624
13.4 virtual components 627
13.4.1 copyright protection vs. customer information 627
13.4.2 design reuse demands better quality and more thorough verification 628
13.4.3 many existing virtual components need to be reworked 629
13.4.4 virtual components require follow-up services 629
13.4.5 indemnification provisions 630
13.4.6 deliverables of a comprehensive vc package 630
13.4.7 business models 631
13.5 the costs of integrated circuits 632
13.5.1 the impact of circuit size 633
13.5.2 the impact of the fabrication process 636
13.5.3 the impact of volume 638
13.5.4 the impact of configurability 639
13.5.5 digest 640
13.6 fabrication avenues for small quantities 642
13.6.1 multi-project wafers 642
13.6.2 multi-layer reticles 643
13.6.3 electron beam lithography 643
13.6.4 laser programming 643
13.6.5 hardwired fpgas and structured asics 644
13.6.6 cost trading 644
13.7 the market side 645
13.7.1 ingredients of commercial success 645
13.7.2 commercialization stages and market priorities 646
13.7.3 service versus product 649
13.7.4 product grading 650
13.8 making a choice 651
13.8.1 asics yes or no? 651
13.8.2 which implementation technique should one adopt? 655
13.8.3 what if nothing is known for sure? 657
13.8.4 can system houses afford to ignore microelectronics? 658
13.9 keys to successful vlsi design 660
13.9.1 project definition and marketing 660
13.9.2 technical management 661
13.9.3 engineering 662
13.9.4 verification 665
13.9.5 myths 665
13.10 appendix: doing business in microelectronics 667
13.10.1 checklists for evaluating business partners and design kits 667
13.10.2 virtual component providers 669
13.10.3 selected low-volume providers 669
13.10.4 cost estimation helps 669
chapter 14 a primer on cmos technology 671
14.1 the essence of mos device physics 671
14.1.1 energy bands and electrical conduction 671
14.1.2 doping of semiconductor materials 672
14.1.3 junctions, contacts, and diodes 674
14.1.4 mosfets 676
14.2 basic cmos fabrication flow 682
14.2.1 key characteristics of cmos technology 682
14.2.2 front-end-of-line fabrication steps 685
14.2.3 back-end-of-line fabrication steps 688
14.2.4 process monitoring 689
14.2.5 photolithography 689
14.3 variations on the theme 697
14.3.1 copper has replaced aluminum as interconnect material 697
14.3.2 low-permittivity interlevel dielectrics are replacing silicon dioxide 698
14.3.3 high-permittivity gate dielectrics to replace silicon dioxide 699
14.3.4 strained silicon and sige technology 701
14.3.5 metal gates bound to come back 702
14.3.6 silicon-on-insulator (soi) technology 703
chapter 15 outlook 706
15.1 evolution paths for cmos technology 706
15.1.1 classic device scaling 706
15.1.2 the search for new device topologies 709
15.1.3 vertical integration 711
15.1.4 the search for better semiconductor materials 712
15.2 is there life after cmos? 714
15.2.1 non-cmos data storage 715
15.2.2 non-cmos data processing 716
15.3 technology push 719
15.3.1 the so-called industry “laws” and the forces behind them 719
15.3.2 industrial roadmaps 721
15.4 market pull 723
15.5 evolution paths for design methodology 724
15.5.1 the productivity problem 724
15.5.2 fresh approaches to architecture design 727
15.6 summary 729
15.7 six grand challenges 730
15.8 appendix: non-semiconductor storage technologies for comparison 731
appendix a elementary digital electronics 732
a.1 introduction 732
a.1.1 common number representation schemes 732
a.1.2 notational conventions for two-valued logic 734
a.2 theoretical background of combinational logic 735
a.2.1 truth table 735
a.2.2 the n-cube 736
a.2.3 karnaugh map 736
a.2.4 program code and other formal languages 736
a.2.5 logic equations 737
a.2.6 two-level logic 738
a.2.7 multilevel logic 740
a.2.8 symmetric and monotone functions 741
a.2.9 threshold functions 741
a.2.10 complete gate sets 742
a.2.11 multi-output functions 742
a.2.12 logic minimization 743
a.3 circuit alternatives for implementing combinational logic 747
a.3.1 random logic 747
a.3.2 programmable logic array (pla) 747
a.3.3 read-only memory (rom) 749
a.3.4 array multiplier 749
a.3.5 digest 750
a.4 bistables and other memory circuits 751
a.4.1 flip-flops or edge-triggered bistables 752
a.4.2 latches or level-sensitive bistables 755
a.4.3 unclocked bistables 756
a.4.4 random access memories (rams) 760
a.5 transient behavior of logic circuits 761
a.5.1 glitches, a phenomenological perspective 762
a.5.2 function hazards, a circuit-independent mechanism 763
a.5.3 logic hazards, a circuit-dependent mechanism 764
a.5.4 digest 765
a.6 timing quantities 766
a.6.1 delay quantities apply to combinational and sequential circuits 766
a.6.2 timing conditions apply to sequential circuits only 768
a.6.3 secondary timing quantities 770
a.6.4 timing constraints address synthesis needs 771
a.7 microprocessor input/output transfer protocols 771
a.8 summary 773
appendix b finite state machines 775
b.1 abstract automata 775
b.1.1 mealy machine 776
b.1.2 moore machine 777
b.1.3 medvedev machine 778
b.1.4 relationships between finite state machine models 779
b.1.5 taxonomy of finite state machines 782
b.1.6 state reduction 783
b.2 practical aspects and implementation issues 785
b.2.1 parasitic states and symbols 785
b.2.2 mealy-, moore-, medvedev-type, and combinational output bits 787
b.2.3 through paths and logic instability 787
b.2.4 switching hazards 789
b.2.5 hardware costs 790
b.3 summary 793
appendix c vlsi designer’s checklist 794
c.1 design data sanity 794
c.2 pre-synthesis design verification 794
c.3 clocking 795
c.4 gate-level considerations 796
c.5 design for test 797
c.6 electrical considerations 798
c.7 pre-layout design verification 799
c.8 physical considerations 800
c.9 post-layout design verification 800
c.10 preparation for testing of fabricated prototypes 801
c.11 thermal considerations 802
c.12 board-level operation and testing 802
c.13 documentation 802
appendix d symbols and constants 804
d.1 mathematical symbols used 804
d.2 abbreviations 807
d.3 physical and material constants 808
references 811
index 832

.　　·Emphasis on synchronous design and HDL code portability
　　·Comprehensive discussion of clocking disciplines
　　·Key concepts behind HDLs without too many syntactical details
　　·A clear focus on the predominant CMOS technology and static circuit style
　　·Just as much semiconductor physics as digital VLSI designers really need to know
　　·Models of industrial cooperation
　　·What to watch out for when purchasing virtual components
　　·Cost and marketing issues of ASICs
　　·Avenues to low-volume fabrication
　　·Largely self-contained (required previous knowledge summarized in two appendices)
　　·Emphasis on knowledge likely to remain useful in the years to come
　　·Many illustrations that facilitate recognizing a problem and the options available
　　·Checklists, hints, and warnings for various situations
　　·A concept proven in classroom teaching and actual design projects
　　A note to instructors
　　Over the past decade, the capabilities of field-programmable logic devices, such as FPGAs and CPLDs, have grown to a point where they have become invaluable ingredients of many electronic products, especially of those designed and marketed by small and medium-sized enterprises. Beginning with the higher levels of abstraction enables instructors to focus on those topics that are equally relevant irrespective of whether a design eventually gcts implemented as a mask-programmed custom chip or from components that are just configured electrically. This material is collected in chapters 1 to 5 of tile book and best taught as part of the Bachelor degree for maximum dissemination. No prior introduction to semiconductors is required. For audiences with little exposure to digital logic and finitc state nmchines, thc material can always be complemented with appendices A and B.
　　Learning how to design mask-programmed VLSI chips is then open to Master students who elect to specialize in the field. Designing electronic circuits down to that level of detail involves many decisions related to electrical, physical, and technological issues. An abstraction to purely logical models is no longer valid since side effects may cause an improperly designed circuit to behave differently than anticipated front digital simulations. How to cope with clock skew, metastability,layout parasitics, ground bounce, crosstalk, leakage, heat, electromigration, latch-up, electrostatic discharge, and process variability in fact makes up nmch of the material from chapter 6 onwards.
　　Again, the top-down organization of the book leaves much freedom as to where to end a class. A shorter course might skip chapter 8 as well as all material on detailed layout design that begins with section 11.5 on the grounds that only few digital designers continue to address device-level issues today. A similar argmnent also applies to the CMOS semiconductor technology introduced in chapter 14. Chapter 13, on the other hand, should not be dropped because, by definition, there are m) engineering projects without economic issues playing a decisive role.
　　For those primarily interested in the business aspects of microelectronics, it is even possible to put together a quick introductory tour from chapters 1, 13, and 15 leaving out all the technicalities associated with actual chip design.
　　The figure below explains how digital VLSI is being taught by the author and his colleagues at the ETH. Probably the best way of preparing for an engineering career in the electronics and microelectronics industry is to complete a design project where circuits are not just being modeled and simulated on a computer but actually fabricated. Provided they come up with a meaningful project proposal, our students are indeed given this opportunity, typically working in teams of two.Following tapeout at the end of the 7th term, chip fabrication via an external multi-project wafer service takes roughly three months. Circuit samples then get systematically tested by their very developers in their 8th and final term. Needless to say that students accepting this offer feel very motivated and that industry highly values the practical experience of graduates formed in this way.The technical descriptions and procedures in this book have been developed with the greatest of care; however, they are provided as is, without warranty of any kind. The author and editors of the book make no warranties, expressed or implied, that the equations, programs, and procedures in this book are free of error, or are consistent with any particular standard of merchantability, or will meet your requirements for any particular application. They should not be relied upon for solving a problem whose incorrect solution could result in injury to a person or loss of property.