数字集成电路——设计透视（影印版·第2版）

.2.2.3 some recurring process steps
2.2.4 simplified cmos process flow
2.3 design rules-the contract between designer and process engineer
2.4 packaging integrated circuits
2.4.1 package materials
2.4.2 interconnect levels
2.4.3 thermal considerations in packaging
2.5 perspective--trends in process technology
2.5.1 short-term developments
2.5.2 in the longer term
2.6 summary
2.7 to probe further
references
design methodology insert a ic layout
a.1 to probe further
references

chapter 3 the devices
3.1 introduction
3.2 the diode
3.2.1 a first glance at the diode--the depletion region
3.2.2 static behavior
3.2.3 dynamic, or transient, behavior
3.2.4 the actual diode--secondary effects
3.2.5 the spice diode model
3.3 the mos(fet) transistor
3.3.1 a first glance at the device
3.3.2 the mos transistor under static conditions
3.3.3 the actual mos transistor---some secondary effects
3.3.4 spice models for the mos transistor
3.4 a word on process variations
3.5 perspective--technology scaling
3.6 summary
3.7 to probe further
references
design methodology insert b circuit simulation
references

chapter 4 the wire
4.1 introduction
4.2 a first glance
4.3 interconnect parameters--capacitance, resistance, and inductance
4.3.1 capacitance
4.3.2 resistance
4.3.3 inductance
4.4 electrical wire models
4.4.1 the ideal wire
4.4.2 the lumped model
4.4.3 the lumped rc model
4.4.4 the distributed rc line
4.4.5 the transmission line spice wire models
4.5.1 distributed rc lines in spice
4.5.2 transmission line models in spice
4.5.3 perspective: a look into the future
4.6 summary
4.7 to probe further
references

part 2 a circuit perspective
chapter 5 the cmos inverter
5.1 introduction
5.2 the static cmos inverter--an intuitive perspective
5.3 evaluating the robustness of the cmos inverter: the static behavior
5.3.1 switching threshold
5.3.2 noise margins
5.3.3 robustness revisited
5.4 performance of cmos inverter: the dynamic behavior
5.4.1 computing the capacitances
5.4.2 propagation delay: first-order analysis
5.4.3 propagation delay from a design perspective
5.5 power, energy, and energy delay
5.5.1 dynamic power consumption
5.5.2 static consumption
5.5.3 putting it all together
5.5.4 analyzing power consumption using spice
5.6 perspective: technology scaling and its impact on the inverter metrics
5.7 summary
5.8 to probe further
references

chapter 6 designing combinational logic gates in cmos
6.1 introduction
6.2 static cmos design
6.2.1 complementary cmos
6.2.2 ratioed logic
6.2.3 pass-transistor logic
6.3 dynamic cmos design
6.3.1 dynamic logic: basic principles
6.3.2 speed and power dissipation of dynamic logic
6.3.3 signal integrity issues in dynamic design
6.3.4 cascading dynamic gates
6.4 perspectives
6.4.1 how to choose a logic style?
6.4.2 designing logic for reduced supply voltages
6.5 summary
6.6 to probe further
references
design methodology insert c how to simulate complex logic
circuits
c.1 representing digital data as a continuous entity
c.2 representing data as a discrete entity
c.3 using higher-level data models
references
design methodology insert d layout techniques for complex gates

chapter 7 designing sequential logic circuits
7.1 introduction
7.1.1 timing metrics for sequential circuits
7.1.2 classification of memory elements
7.2 static latches and registers
7.2.1 the bistability principle
7.2.2 multiplexer-based latches
7.2.3 master-slave edge-triggered register
7.2.4 low-voltage static latches
7.2.5 static sr flip-flops writing data by pure force
7.3 dynamic latches and registers
7.3.1 dynamic transmission-gate edge-triggered registers
7.3.2 c2mos--a clock-skew insensitive approach
7.3.3 true single-phase clocked register (tspcr)
7.4 alternative register styles*
7.4.1 pulse registers
7.4.2 sense-amplifier-based registers
7.5 pipelining: an approach to optimize sequential circuits
7.5.1 latch- versus register-based pipelines
7.5.2 nora-cmos---a logic style for pipelined structures
7.6 nonbistable sequential circuits
7.6.1 the schmitt trigger
7.6.2 monostable sequential circuits
7.6.3 astable circuits
7.7 perspective: choosing a clocking strategy
7.8 summary
7.9 to probe further
references

part 3 a system perspective
chapter 8 implementation strategies for digital ics
8.1 introduction
8.2 from custom to semicustom and structured-array design approaches
8.3 custom circuit design
8.4 cell-based design methodology
8.4.1 standard cell
8.4.2 compiled cells
8.4.3 macrocells, megacells and intellectual property
8.4.4 semicustom design flow
8.5 array-based implementation approaches
8.5.1 prediffused (or mask-programmable) arrays
8.5.2 prewired arrays
8.6 perspective the implementation platform of the future
8.7 summary
8.8 to probe further
references
design methodology insert e characterizing logic and sequential
cells
references
design methodology insert f design synthesis
references

chapter 9 coping with interconnect
9.1 introduction
9.2 capacitive parasitics
9.2.1 capacitance and reliability---cross talk
9.2.2 capacitance and performance in cmos
9.3 resistive parasitics
9.3.1 resistance and reliability--ohmic voltage drop
9.3.2 electromigration
9.3.3 resistance and performance--rc delay
9.4 inductive parasitics*
9.4.1 inductance and reliability-- voltage drop
9.4.2 inductance and performance transmission-line effects
9.5 advanced interconnect techniques
9.5.1 reduced-swing circuits
9.5.2 current-mode transmission techniques
9.6 perspective: networks-on-a-chip
9.7 summary
9.8 to probe further
references

chapter 10 timing issues in digital circuits
10.1 introduction
10.2 timing classification of digital systems
10.2.1 synchronous interconnect
10.2.2 mesochronous interconnect
10.2.3 plesiochronous interconnect
10.2.4 asynchronous interconnect
10.3 synchronous design--an in-depth perspective
10.3.1 synchronous timing basics
10.3.2 sources of skew and jitter
10.3.3 clock-distribution techniques
10.3.4 latch-based clocking
10.4 self-timed circuit design*
10.4.1 self-timed logic--an asynchronous technique
10.4.2 completion-signal generation
10.4.3 self-timed signaling
10.4.4 practical examples of self-timed logic
10.5 synchronizers and arbiters*
10.5.1 synchronizers---concept and implementation
10.5.2 arbiters
10.6 clock synthesis and synchronization using a phase-locked loop*
10.6.1 basic concept
10.6.2 building blocks of a pll
10.7 future directions and perspectives
10.7.1 distributed clocking using dlls
10.7.2 optical clock distribution
10.7.3 synchronous versus asynchronous design
10.8 summary
10.9 to probe further
references
design methodology insert g design verification
references

chapter 11 designing arithmetic building blocks
11.1 introduction
11.2 datapaths in digital processor architectures
11.3 the adder
11.3.1 the binary adder: definitions
11.3.2 the full adder: circuit design considerations
11.3.3 the binary adder: logic design considerations
11.4 the multiplier
11.4.1 the multiplier: definitions
11.4.2 partial-product generation
11.4.3 partial-product accumulation
11.4.4 final addition
11.4.5 multiplier summary
11.5 the shifter
11.5.1 barrel shifter
11.5.2 logarithmic shifter
11.6 other arithmetic operators
11.7 power and speed trade-offs in datapath structures*
11.7.1 design time power-reduction techniques
11.7.2 run-time power management
11.7.3 reducing the power in standby (or sleep) mode
11.8 perspective: design as a trade-off
11.9 summary
11.10 to probe further
references

chapter 12 designing memory and array structures
12.1 introduction
12.1.1 memory classification
12.1.2 memory architectures and building blocks
12.2 the memory core
12.2.1 read-only memories
12.2.2 nonvolatile read-write memories
12.2.3 read-write memories (ram)
12.2.4 contents-addressable or associative memory (cam)
12.3 memory peripheral circuitry*
12.3.1 the address decoders
12.3.2 sense amplifiers
12.3.3 voltage references
12.3.4 drivers/buffers
12.3.5 timing and control
12.4 memory reliability and yield*
12.4.1 signal-to-noise ratio
12.4.2 memory yield
12.5 power dissipation in memories*
12.5.1 sources of power dissipation in memories
12.5.2 partitioning of the memory
12.5.3 addressing the active power dissipation
12.5.4 data-retention dissipation
12.5.5 summary
12.6 case studies in memory design
12.6.1 the programmable logic array (pla)
12.6.2 a 4-mbit sram
12.6.3 a 1-gbit nand flash memory
12.7 perspective: semiconductor memory trends and evolutions
12.8 summary
12.9 to probe further
references

design methodology insert h validation and test of manufactured circuits
h. 1 introduction
h.2 test procedure
h.3 design for testability
h.3.1 issues in design for testability
h.3.2 ad hoc testing
h.3.3 scan-based test
h.3.4 boundary-scan design
h.3.5 built-in self-test (bist)
h.4 test-pattern generation
h.4.1 fault models
h.4.2 automatic test-pattern generation (atpg)
h.4.3 fault simulation
h.5 to probe further
references
problem solutions
indexs

.　　 Course with systems focus:
　　 1, (2, 3), 4, 5, 6, 7, 8, 9, 10.1-10.4, 11, 12.1-12.2.
　　 The design methodology inserts are, by preference, covered in concurrence with the chapter to which they are attached.
　　 In order to maintain a consistent flow through each of the chapters, the topics are introduced first, followed by a detailed and in-depth discussion of the ideas. A Perspective section discusses how the introduced concepts relate to real world designs and how they might be impacted by future evolutions. Each chapter finishes with a Summary, which briefly enumerates the topics covered in the text, followed by To Probe Further and Reference sections. These provide ample references and pointers for a reader interested in further details on some of the material.
　　 As the title of the book implies, one of the goals of this book is to stress the design aspect of digital circuits. To achieve this more practical viewpoint and to provide a real perspective, we have interspersed actual design examples and layouts throughout the text. These case studies help to answer questions, such as "How much area or speed or power is really saved by applying this technique?" To mimic the real design process, we are making extensive use of design tools such as circuitand switch-level simulation as well as layout editing and extraction. Computer analysis is used throughout to verify manual results, to illustrate new concepts, or to examine complex behavior beyond the reach of manual analysis.
　　 Finally, to facilitate the learning process, there are numerous examples included in the text. Each chapter contains a number of problems or brain-teasers (answers for which can be found in the back of the book), that provoke thinking and understanding while reading.
　　 The Worldwide Web Companion
　　 A worldwide web companion (http://bwrc. eecs. berkeley, edu/IcBook/index. htm) provides fully worked-out design problems and a complete set of overhead transparencies, extracting the most important figures and graphs from the text.
　　 In contrast to the first edition, we have chosen NOT to include problems sets and design problems in the text. Instead we decided to make them available on the book's web site. This gives us the opportunity to dynamically upgrade and extend the problems, providing a more effective tool for the instructor. More than 300 challenging exercises are currently provided. The goal is to provide the individual reader an independent gauge for his understanding of the mate rial and to provide practice in the use of some of the design tools. Each problem is keyed to the text sections it refers to (e.g., [1.3]), the design tools that must be used when solving the problem (e.g., SPICE) and a rating, ranking the problems on difficulty: (E) easy, (M) moderate, and (C) challenging. Problems marked with a (D) include a design or research elements. Solutions to the problem sets are available only to instructors of academic institutions that have chosen to adopt our book for classroom use. They are available through the publisher on a password protected web site.
　　 Open-ended design problems help to gain the ail-important insight into design optimization and trade-off. The use of design editing, verification and analysis tools is recommended when attempting these design problems. Fully worked out versions of these problems can be found on the web site.
　　 In addition, the book's web site also offers samples of hardware and software laboratories, extra background information, and useful links.
　　Compelling Features of the Book
　　 · Brings both circuit and systems views on design together. It offers a profound understanding of the design of complex digital circuits, while preparing the designer for new challenges that might be waiting around the comer.
　　 · Design-oriented perspectives are advocated throughout. Design challenges and guidelines are highlighted. Techniques introduced in the text are illustrated with real designs and complete SPICE analysis.
　　 · Is the first circuit design book that focuses solely on deep-submicron devices. To facilitate this, a simple transistor model for manual analysis, called the unified MOS model, has been developed.
　　 · Unique in showing how to use the latest techniques to design complex high-performance or low-power circuits. Speed and power treated as equal citizens throughout the text.
　　 · Covers crucial reai-world system design issues such as signal integrity, power dissipation, interconnect, packaging, timing, and synchronization.
　　 · Provides unique coverage of the latest design methodologies and tools, with a discussion of how to use them from a designers' perspective.
　　 · Offers perspectives on how digital circuit technology might evolve in the future.
　　 · Outstanding illustrations and a usable design-oriented four-color insert.
　　 · To Probe Further and Reference sections provide ample references and pointers for a reader interested in further details on some of the material.
　　 · Extensive instructional package is available over the intemet from the author's web site.
　　 Includes design software, transparency masters, problem sets, design problems, actual layouts, and hardware and software laboratories.
　　 The Contents at a Glance
　　 A quick scan of the table of contents shows how the ordering of chapters and the material covered are consistent with the advocated design methodology. Starting from a model of the semiconductor devices, we will gradually progress upwards, covering the inverter, the complex logic gate (NAND, NOR, XOR), the functional (adder, multiplier, shifter, register) and the system module (datapath, controller, memory) levels of abstraction. For each of these layers, the dominant design parameters are identified and simplified models are constructed, abstracting away the nonessential details. While this layered modeling approach is the designer's best handle on complexity, it has some pitfalls. This is illustrated in Chapters 9 and 10, where topics with a global impact, such as interconnect parasitics and chip timing, are discussed. To further express the dichotomy between circuit and system design visions, we have divided the book contents into two major parts: Part II (Chapters 4-7) addresses mostly the circuit perspective of digital circuit design, while Part IH (Chapters 8-12) presents a more system oriented vision. Part I (Chapters 1-4) provides the necessary foundation (design metrics, the manufacturing process, device and interconnect models).
　　 Chapter 1 serves as a global introduction. After a historical overview of digital circuit design, the concepts of hierarchical design and the different abstraction layers are introduced. A number of fundamental metrics, which help to quantify cost, reliability, and performance of a design, are introduced.
　　 Chapter 2 provides a short and compact introduction to the MOS manufacturing process. Understanding the basic steps in the process helps to create the three-dimensional understanding of the MOS transistor, which is crucial when identifying the sources of the device parasitics. Many of the variations in device parameters can also be attributed to the manufacturing process as well. The chapter further introduces the concept of design rules, which form the interface between the designer and the manufacturer. The chapter concludes with an overview of the chip packaging process, an often-overlooked but crucial element of the digital IC design cycle.
　　 Chapter 3 contains a summary of the primary design building blocks, the semiconductor devices. The main goal of this chapter is to provide an intuitive understanding of the operation of the MOS as well as to introduce the device models, which are used extensively in the later chapters. Major attention is paid to the artifacts of modem submicron devices, and the modeling thereof. Readers with prior device knowledge can traverse this material rather quickly.
　　 Chapter 4 contains a careful analysis of the wire, with interconnect and its accompanying parasitics playing a major role. We visit each of the parasitics that come with a wire(capacitance, resistance, and inductance) in mm. Models for both manual and computer analysis are introduced.
　　 Chapter 5 deals with the nucleus of digital design, the inverter. First, a number of fundamental properties of digital gates are introduced. These parameters, which help to quantify the performance and reliability of a gate, are derived in detail for two representative inverter stmctures: the static complementary CMOS. The techniques and approaches introduced m this chapter are of crucial importance, as they are repeated over and over again in the analysis of other gate structures and more complex gate structures.
　　 In Chapter 6 this fundamental knowledge is extended to address the design of simple and complex digital CMOS gates, such as NOR and NAND structures. It is demonstrated that, depending upon the dominant design constraint (reliability, area, performance, or power), other CMOS gate structures besides the complementary static gate can be attractive. The properties of a number of contemporary gatelogic families are analyzed and compared. Techniques to optimize the erformance and power consumption of complex gates are introduced.
　　 Chapter 7 discusses how memory function can be accomplished using either positive feedback or charge storage. Besides analyzing the traditional bistable flip-flops, other equential circuits such as the mono- and astable multivibrators are also introduced. All chapters prior to Chapter 7 deal exclusively with combinational circuits, that is circuits without a sense of the past history of the system. Sequential logic circuits, in contrast, can remember and store the
　　past state.
　　 All chapters preceding Chapter 8 present a circuit-oriented approach towards digital design. The analysis and optimization process has been constrained to the individual gate. In this chapter, we take our approach one step further and analyze how gates can be connected together to form the building blocks of a system. The system-level part of the book starts, appropriately, with a discussion of design methodologies. Design automation is the only way to cope with the ever-increasing complexity of digital designs. In Chapter 8, the prominent ways of producing large designs in a limited time are discussed. The chapter spends considerable time on the different implementation methodologies available to today's designer. Custom versus semi-custom, hardwired yersus fixed, regular array versus ad-hoc are some of the issues put forward.
　　 Chapter 9 revisits the impact of interconnect wiring on the functionality and performance of a digital gate. A wire introduces parasitic capacitive, resistive, and inductive effects, which are becoming ever more important with the scaling of the technology. Approaches to minimize the impact of these interconnect parasitics on performance, power dissipation and circuit reliability are introduced. The chapter also addresses some important issues such as supply-voltage distribution, and input/output circuitry.
　　 In Chapter 10 details how that in order to operate sequential circuits correctly, a strict ordering of the switching events has to be imposed. Without these timing constraints, wrong data might be written into the memory cells. Most digital circuits use a synchronous, clocked approach to impose this ordering. In Chapter 10, the different approaches to digital circuit timing and clocking are discussed. The impact of important effects such as clock skew on the behavior of digital synchronous circuits is analyzed. The synchronous approach is contrasted with alternative techniques, such as selftimed circuits. The chapter concludes with a short introduction to synchronization and clock-generation circuits.
　　 In Chapter 11, the design of a variety of complex arithmetic building blocks such as adders, multipliers, and shifters, is discussed. This chapter is crucial because it demonstrates
　　how the design techniques introduced in chapters 5 and 6 are extended to the next abstraction layer. The concept of the critical path is introduced and used extensively in the performance analysis and optimization. Higher-level performance models are derived. These help the designer to get a fundamental insight into the operation and quality of a design module, without having to resort to an in-depth and detailed analysis of the underlying circuitry.
　　 Chapter 12 discusses in depth the different memory classes and their implementation. Whenever large amounts of data storage are needed, the digital designer resorts to special circuit modules, called memories. Semiconductor memories achieve very high storage density by compromising on some of the fundamental properties of digital gates. Instrumental in the design of reliable and fast memories is the implementation of the peripheral circuitry, such as the decoders, sense amplifiers, drivers, and control circuitry, which are extensively covered. Finally, as the primary issue in memory design is to ensure that the device works consis tently under all operating circumstances, the chapter concludes with a detailed discussion of memory reliability. This chapter as well as the previous one are optional for undergraduate courses.
　　 Acknowledgments
　　 The authors would like to thank all those who contributed to the emergence, creation and correction of this manuscript. First of all, thanks to all the graduate students that helped over the years to bring the text to where it is today. Thanks also to the students of the eecsl41 and eecs241 courses at Berkeley and the 6.374 course at MIT, who suffered through many of the experimental class offerings based on this book. The feedback from instructors, engineers, and students from all Qver the world has helped tremendously in focusing the directions of this new edition, and in fine-tuning the final text. The continuous stream of e-mails indicate to us that we are on the right track.
　　 In particular, we would like to acknowledge the contributions of Mary-Jane Irwin, Vijay Narayanan, Eby Friedman, Fred Rosenberger, Wayne Bufieson, Shekhar Borkar, Ivo Bolsens, Duane Boning, Olivier Franza, Lionel Kimerling, Josie Ammer, Mike Sheets, Tufan Karalar, Huifang Qin, Rhett Davis, Nathan Chan, Jeb Durant, Andrei Vladinfirescu, Radu Zlatanovici, Yasuhisa Shimazaki, Fujio Ishihara, Dejan Markovic, Vladimir Stojanovic, SeongHwan Cho, James Kao, Travis Simpkins, Siva Narendra, James Goodman, Vadim Gutnik, Theodoros Konstantakopoulos, Rex Min, Vikas Mehrotra, and Paul-Peter Sotiriadis. Their help, input, and feedback are greatly appreciated. Obviously, we remain thankful to those who helped create and develop the first edition.
　　 I am extremely grateful to the staff at Prentice Hall, who have been instrumental in turning a rough manuscript into an enjoyable book. First of all, I would like to acknowledge the help and constructive feedback of Tom Robbins, Publisher, Daniel Sandin, Production Editor, and David George, Managing Editor. A special word of thanks to Brenda Vanoni at Berkeley, for her invaluable help in the copy editing and the website creation process. The web expertise of Carol Sitea came in very handy as well.
　　 I would like to highlight to role of computer aids in developing this manuscript. All drafts were completely developed on the FrameMaker publishing system (Adobe Systems). Graphs were mostly created using MATLAB. Microsoft Frontpage is the tool of choice for the web-page creation. For circuit simulations, we used HSPICE (Avant!). All layouts were generated using the Cadence physical design suite.
　　 Finally, some words of gratitude to the people that had to endure the creation process of this book, Kathelijn, Karthiyayani, Krithivasan, and Rebecca. While the generation of a new edition brings substantially less pain than a first edition, we consistently underestimate what it takes, especially in light of the rest of our daily loads. They have been a constant support, help and encouragement during the writing of this manuscript.
　　JAN M. RABAEY
　　ANANTHA CHANDRAKASAN
　　BORIVOJE NIKOLIC
　　Berkeley, Calistoga, Cambridge