数字集成电路：电路、系统与设计(第二版.英文版)

Chapter 3 The Devices
3.1 Introduction
3.2 The Diode
3.3 The MOS(FET) Transistor
3.4 A Word on Process Variations
3.5 Perspective--Technology Scaling
3.6 Summary
3.7 To Probe Further
References
Design Methodology Insert B Circuit Simulation
References
Chapter 4 The Wire
4.1 Introduction
4.2 A First Glance
4.3 Interconnect Parameters----Capacitance, Resistance,
and Inductance
4.4 Electrical Wire Models
4.5 SPICE Wire Models
4.6 Summary
4.7 To Probe Further
References
Part 2 A Circuit Perspective
Chapter 5 The CMOS Inverter
5.1 Introduction
5.2 The Static CMOS Inverter--An Intuitive Perspective
5.3 Evaluating the Robusmess of the CMOS Inverter:
5.4 Performance of CMOS Inverter: The Dynamic Behav
5.5 Power, Energy, and Energy Delay
5.6 Perspective: Technology Scaling and its Impact
on the Inverter Metrics
5.7 Summary
5.8 To Probe Further
References
Chapter 6 Designing Combinational Logic Gates in CMOS
6.1 Introduction
6.2 Static CMOS Design
6.3 Dynamic CMOS Design
6.4 Perspectives
6.5 Summary
6.6 To Probe Further
References
Design Methodology Insert C How to Simulate Complex
Logic Circuits
C. 1 Representing Digital Data as a Continuous Entity
C.2 Representing Data as a Discrete Entity
C.3 Using Higher-Level Data Models
References
Design Methodology Insert D Layout Techniques for Complex Gates
Chapter 7 Designing Sequential Logic Circuits
7.1 Introduction
7.2 Static Latches and Registers
7.3 Dynamic Latches and Registers
7.4 Alternative Register Styles'
7.5 Pi?lining: An Approach to Optimize Sequential Circuits
7.6 Nonbistable Sequential Circuits
7.7 Perspective: Choosing a Clocking Strategy
7.8 Summary
7.9 To Probe Further
References
Part 3 A System Perspective
Chapter 8 Implementation Strategies for Digital ICS
8.1 Introduction
8.2 From Custom to Semicustom and Structured-Array Design Approaches
8.3 Custom Circuit Design
8.4 Cell-Based Design Methodology
8.5 Array-Based Implementation Approaches
8.6 Perspective--The Implementation Platform of th,
8.7 Summary
8.8 To Probe Further
References
Design Methodology Insert E Characterizing Logic and Sequential Cells
References
Design Methodology Insert F Design Synthesis
References
Chapter 9 Coping with Interconnect
9.1 Introduction
9.2 ' Capacitive Parasitics
9.3 ResistiveParasitics
9.4 Inductive Parasitics
9.5 Advanced Interconnect Techniques
9.6 Perspective: Networks-on-a-Chip
9.7 Summary
9.8 To Probe Further
References
Chapter 10 Timing Issues in Digital Circuits
10.1 Introduction
10.2 Timing Classification of Digital Systems
10.3 Synchronous DesignwAn In-depth Perspective
10.4 Self-Timed Circuit Design*
10.5 Synchronizers and Arbiters*
10.6 Clock Sy_nthesis and Synchronization Using
10.7 Future Directions and Perspectives
10.8 Summary
10.9 To Probe Further
References
Design Methodology Insert G Design Verification
References
Chapter 11 Designing Arithmetic Building Blocks
11.1 Introduction
11.2 Datapaths in Digital Processor Architectures
11.3 The Adder
11.4 The Multiplier
11.5 The Shifter
11.6 Other Arithmetic Operators
11.7 Power and Speed Trade-offs in Datapath Str
11.8 Perspective: Design as a Trade-off
11.9 Summary
11.10 To Probe Further
References
Chapter 12 Designing Memory and Array Structures
12.1 Introduction
12.2 The Memory 2ore
12.3 Memory Peripheral Circuitry*
12.4 Memory Reliability and Yield*
12.5 Power Dissipation in Memories*
12.6 Case Studies in Memory Design
12.7 Perspective: Semiconductor Memory Trends and Evolutions
12.8 Summary
12.9 To Probe Further
References
Design Methodology Insert H Validation and Test of Manufactured Circuits
H.1 Introduction
H.2 Test Procedure
H.3 Design for Testability
H.4 Test-Pattern Generation
H.5 To Probe Further
References
Problem Solutions
Index