专用集成电路时序验证(英文影印版)

.2.3.3 timing specifications
2.3.4 timing checks
2.4 timing analysis of phase-locked loops
2.4.1 pll basics
2.4.2 pll ideal behavior
2.4.3 pll errors
8 timing in asics
3.1 introduction
3.2 prelayout timing
3.2.1 rtl vs. gate-level timing
3.2.2 timing in rtl code
3.2.3 delay with a continuous assignment statement
3.2.4 delay in a process statement
3.2.6 intra-assignment delays
3.2.6 the verilog specify block
3.2.7 timing in-gate level code
3.2.8 synthesis and timing constraints
3.2.9 design rule constraints
3.2.10 optimization constraints
3.2.11 gate and wire-load models
3.2.12 the synthesis flow
3.2.13 synthesis tips
3.2.14 back annotation to gate-level rtl
3.3 post. layout timing
3.3.1 man-a1 line-propagation delay calculations
3.3.2 signal-line capacitance calculation
3.3.3 signal line resistance calculation
3.3.4 signal trace rc delay evaluation
3.4 asic sign-off checklist
3.4.1 library development
3.4.2 functional specification
3.4.3 rtl coding
3.4.4 simulations of rtl
3.4.5 logic synthesis
3.4.6 test insertion and atpg
3.4.7 postsynthesis gate-level simulation or static timing analysis
3.4.8 floorplsnning
3.4.9 place and route
3.4.10 final verification of the extracted netlist ..
3.4.11 mask generation and fabrication
3.4.12 testing
4 programmable logic based design
4.1 introduction
4.2 programmable logic structures
4.2.1 logic block
4.2.2 input/output block
4.2.3 routing facilities
4.3 design flow
4.4 timing parameters
4.4.1 timing derating factors
4.4.2 grading programmable logic devices by speed
4.4.3 beet-case delay values
4.5 timing analysis
4.5.1 actel act fpga fsmily
4.5.2 actel act 3 architecture
4.5.3 actel act 3 timing model
4.5.4 altera flex 8000
4.5.5 altera flex 8000 architecture
4.5.6 altera flex 8000 timing model
4.5.7 xilinx xc3000/xc4000 fpga families
4.5.8 xilinx xc9500 cpld
4.5.9 xilinx xc9500 cpld architecture
4.5.10 xilinx xc9500 cpld timing model
4.6 hdl synthesis
4.7 software development systems
4.7.1 timing constraints
4.7.2 operating conditions
4.7.3 static timing analysis
4.7.4 vendor-specific timing-verification tools
4.7.5 actel designer
4.7.6 altera max+plus ii
4.7.7 xilinx xact/m1
a primetime
b pearl
c timingdesigner
d transistor-level timing verification
references
index
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