高速CMOS电路设计:Logical Effort方法(英文影印版)

.3.6　using the wrong gate size　59
3.7　summary　61
3.8　exercises　61
4　calculating the logical effort of gates　63
4.1　definitions of logical effort　64
4.2　grouping input signals　65
4.3　calculating logical effort　66
4.4　asymmetric logic gates　69
4.5　catalog of logic gates　71
4.6　estimating parasitic delay　80
4.7　properties of logical effort　82
4.8　exercises　83
5　calibrating the model　87
5.1　calibration technique　87
5.2　designing test circuits　90
5.3　other characterization methods　98
5.4　calibrating special circuit families　101
5.5　summary　102
5.6　exercises　102
6　asymmetric logic gates　105
6.1　designing asymmetric logic gates　105
6.2　applications of asymmetric logic gates　109
6.3　summary　113
6.4　exercises　113
7　unequal rising and falling delays　115
7.1　analyzing delays ..116
7.2　case analysis　120
7.3　optimizing cmos p/n ratios　125
7.4　summary　127
7.5　exercises　128
8　circuit families　129
8.1　pseudo-nmos circuits　130
8.2　domino circuits　133
8.3　transmission gates　146
8.4　summary　148
8.5　exercises　149
9　forks of amplifiers　151
9.1　the fork circuit form　152
9.2　how many stages should a fork use?　155
9.3　summary　160
9.4　exercises　161
10　branches and interconnect　163
10.1　circuits that branch at a single input　164
10.2 branches after logic　170
10.3 circuits that branch and recombine　172
10.4 interconnect　175
10.5 a design approach　177
10.6 exercises　179
11　wide structures　181
11.1 an n-input and structure　181
11.2 an n-input muller c-element　186
11.3 decoders　191
11.4 multiplexers　196
11.5 summary　202
11.6 exercises　203
12　conclusions　205
12.1 the theory of logical effort　205
12.2 insights from logical effort　208
12.3 a design procedure　210
12.4 other approaches to path design　213
12.5 shortcomings of logical effort　215
12.6 parting words　216
appendices
a　cast of characters
b　reference process parameters
c　solutions to selected exercises
bibliography　233
index ...235